Patents by Inventor Kazumasa Sunouchi

Kazumasa Sunouchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9728242
    Abstract: According to one embodiment, a memory device includes a spin transfer torque magnetoresistive element including a first magnetic layer, a second magnetic layer, and a nonmagnetic layer between the first magnetic layer and the second magnetic layer, a temperature detecting unit detecting an ambient temperature of the magnetoresistive element, and a write voltage generating unit generating a write voltage for the magnetoresistive element in accordance with the temperature detected by the temperature detecting unit.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: August 8, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Motoyuki Sato, Kazumasa Sunouchi, Keisuke Nakatsuka
  • Patent number: 6980463
    Abstract: A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: December 27, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Kazumasa Sunouchi
  • Patent number: 6632723
    Abstract: A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: October 14, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama
  • Patent number: 6590244
    Abstract: A memory cell section includes a first wiring which is extended in a first direction, and a second wiring which is extended in a second direction different from the first direction, and a third wiring which is disposed between the first and second wirings, and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings. Further, a peripheral circuit section includes a fourth wiring, and a fifth wiring which is disposed above the fourth wiring, and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as a resistive element.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: July 8, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiaki Asao, Kazumasa Sunouchi, Kentaro Nakajima
  • Patent number: 6483138
    Abstract: A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: November 19, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Habu, Kazumasa Sunouchi, Masami Aoki, Tahru Ozaki
  • Publication number: 20020160581
    Abstract: A semiconductor device is disclosed, which comprises a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.
    Type: Application
    Filed: April 26, 2002
    Publication date: October 31, 2002
    Inventors: Shinichi Watanabe, Takashi Ohsawa, Kazumasa Sunouchi, Yoichi Takegawa, Takeshi Kajiyama
  • Publication number: 20020140060
    Abstract: A memory cell section includes a first wiring which is extended in a first direction, and a second wiring which is extended in a second direction different from the first direction, and a third wiring which is disposed between the first and second wirings, and a first magneto resistive effect element which is disposed at an intersection of the first and second wirings between the first and second wirings, and is connected to the second and third wirings. Further, a peripheral circuit section includes a fourth wiring, and a fifth wiring which is disposed above the fourth wiring, and a second magneto resistive effect element which is disposed between the fourth and fifth wirings and is connected to the fourth and fifth wirings to be used as a resistive element.
    Type: Application
    Filed: March 21, 2002
    Publication date: October 3, 2002
    Inventors: Yoshiaki Asao, Kazumasa Sunouchi, Kentaro Nakajima
  • Publication number: 20020141233
    Abstract: A semiconductor memory device includes a first magneto resistive element disposed in a memory cell portion, a first circuit disposed in the memory cell portion, the first circuit writing data into the first magneto resistive element or reading out data from the first magneto resistive element, and at least a portion of a second circuit disposed in a region below the memory cell portion.
    Type: Application
    Filed: March 28, 2002
    Publication date: October 3, 2002
    Inventors: Keiji Hosotani, Kazumasa Sunouchi
  • Patent number: 6300178
    Abstract: The present invention simplifies a manufacturing process by performing contact hole formation in a single step even in manufacturing a device having a self alignment contact. A cap layer having a contact portion is formed in a self alignment manner on a gate electrode formed on a silicon substrate. After a SiO2 interlayer film is deposited on the cap layer and the silicon substrate, the patterning of a contact hole is performed. Thereafter, a wiring layer is formed in the contact hole. The diameter of the contact portion is formed differently from the diameter of the contact hole.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: October 9, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazumasa Sunouchi
  • Patent number: 6294422
    Abstract: In a stack type memory cell of 8F2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: September 25, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Sunouchi, Masami Aoki
  • Patent number: 6258650
    Abstract: A semiconductor memory device includes a substrate, a first insulation layer formed on the substrate, a plurality of bit lines arranged on the first insulation layer, a second insulation layer formed all over the bit lines and having a plurality of first openings, an element isolating region formed on the second insulation layer, a plurality of island-like element forming semiconductor regions formed as surrounded by the element isolating region, a plurality of transistors respectively formed in the element forming semiconductor regions, and a plurality of capacitors respectively formed on the transistors. Each of the transistors includes a gate electrode insulatively formed on the element forming region, and a first and a second diffusion region formed on either side of the gate electrode, the first diffusion region being connected to a corresponding one of the bit lines through a via conductor formed in one of the first openings.
    Type: Grant
    Filed: December 14, 1999
    Date of Patent: July 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazumasa Sunouchi
  • Patent number: 6204527
    Abstract: A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: March 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Sudo, Kazumasa Sunouchi, Akihiro Nitayama
  • Patent number: 6153476
    Abstract: In a DRAM, a plurality of first MOSFETs are formed in a cell region on a semiconductor substrate based on the minimum design rule, and a first gate side-wall having a side-wall insulation film is formed on the side-wall portion of a first gate electrode of each of the first MOSFETs. At least one second MOSFET is formed in a peripheral circuit region on the semiconductor substrate, and a second gate side-wall having side-wall insulation films is formed on the side-wall portion of a second gate electrode of the second MOSFET. Both the first MOSFETs, which is capable of forming a fine contact hole self-aligned with the first gate electrode, and the second MOSFET, which is capable of sufficiently mitigating the parasitic resistance while suppressing the short channel effect, can be formed on the same substrate.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Satoshi Inaba, Tohru Ozaki, Yusuke Kohyama, Kazumasa Sunouchi
  • Patent number: 6078073
    Abstract: A gate electrode having a first insulating film laminated in the upper portion thereof is formed on a gate insulating film formed on a semiconductor substrate. A side wall is formed on the side wall of the gate electrode, and an insulating film is formed to cover the gate electrode and the side wall. Ion implantation is performed through the insulating film so that a diffusion layer is formed on the semiconductor substrate. An interlayer dielectric film is formed, and then the interlayer dielectric film and the insulating film are selectively etched so that an opening portion for exposing the gate insulating film is formed in a self-align manner with the gate electrode. Then, the gate insulating film in the bottom portion of the opening portion is removed so that the surface of the semiconductor substrate is exposed. Then, a wiring layer connected to the exposed surface of the semiconductor substrate is formed.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: June 20, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Habu, Kazumasa Sunouchi, Masami Aoki, Tohru Ozaki
  • Patent number: 6031260
    Abstract: A semiconductor memory device includes a substrate, a first insulation layer formed on the substrate, a plurality of bit lines arranged on the first insulation layer, a second insulation layer formed all over the bit lines and having a plurality of first openings, an element isolating region formed on the second insulation layer, a plurality of island-like element forming semiconductor regions formed as surrounded by the element isolating region, a plurality of transistors respectively formed in the element forming semiconductor regions, and a plurality of capacitors respectively formed on the transistors. Each of the transistors includes a gate electrode insulatively formed on the element forming region, and a first and a second diffusion region formed on either side of the gate electrode, the first diffusion region being connected to a corresponding one of the bit lines through a via conductor formed in one of the first openings.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: February 29, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazumasa Sunouchi
  • Patent number: 6025623
    Abstract: In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: February 15, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Sunouchi, Masami Aoki
  • Patent number: 5559350
    Abstract: A dynamic RAM array comprises a substrate, a plurality of semiconductor island regions and a trench region formed on the substrate, each island region being surrounded by the trench region, and the trench region having wider trench portions and narrower trench portions, an insulating layer formed on the trench region, capacitors refilled in the wider trench portions, each capacitor having a plate electrode, a capacitor insulating layer and a storage node electrode, refilled layers formed in the narrower trench portion, for forming field isolation regions, MOS transistors formed on the island region, each MOS transistor having a source, a drain and a gate as word line, one of the source and drain being coupled with the storage node electrode, and bit lines perpendicular to the word line, being coupled with the other of the source and drain.
    Type: Grant
    Filed: November 29, 1994
    Date of Patent: September 24, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Thoru Ozaki, Kazumasa Sunouchi, Seiichi Takedai, Yoshiyuki Shioyama
  • Patent number: 5488242
    Abstract: In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: January 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Sunouchi, Hiroshi Takato, Tohru Ozaki, Naoko Okabe, Katsuhiko Hieda, Fumio Horiguchi, Akihiro Nitayama, Takashi Yamada, Kouji Hasimoto, Satosi Inoue
  • Patent number: 5363325
    Abstract: A bipolar transistor Q.sub.1 having a collector formed of a substrate region SUB of a MOS transistor M.sub.1, a base formed of the drain region of the MOS transistor and an emitter formed on the base and connected to a bit line BL is connected between the bit line BL and a memory cell MC formed of the MOS transistor M.sub.1 and and a capacitor C.sub.1 and the current amplifying operation of a bipolar transistor is used for data readout.
    Type: Grant
    Filed: July 1, 1992
    Date of Patent: November 8, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Sunouchi, Tsuneaki Fuse, Akihiro Nitayama, Takehiro Hasegawa, Shigeyoshi Watanabe, Fumio Horiguchi, Katsuhiko Hieda
  • Patent number: 5248628
    Abstract: A semiconductor memory device wherein at least one of a storage node contact hole and a bit line contact hole includes a first contact hole made in a first inter-layer insulating film formed over a gate electrode and a second contact hole made in a second inter-layer insulating film formed over an electrically conductive material embedded up to a level higher than the gate electrode in the first contact hole which is contacted with the electrically conductive material, the conductive material being exposed by etching a part of the second inter-layer insulating film, whereby the size of the memory device can be made small and the reliability can be improved. Further, a capacitor is formed in a layer higher than a bit line thereby to facilitate the processing of a storage node electrode to increase the capacitor area and to improve the reliability since it is unnecessary to carry out patterning a plate electrode within a cell array.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: September 28, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Naoko Okabe, Satoshi Inoue, Kazumasa Sunouchi, Takashi Yamada, Akihiro Nitayama, Hiroshi Takato