Abstract: A method of generating an IC layout diagram includes dividing a column of NOR-type read-only memory (ROM) bit cells into a plurality of N-bit groups separated by isolation features, wherein each group includes the number of bits N greater than two, based on a ROM code programming pattern of the column, assigning one or more logic patterns to each N-bit group of the plurality of N-bit groups, and storing an IC layout diagram including the logic patterns in a storage device.

Abstract: A semiconductor device includes a memory array comprising a plurality of transistors arranged over a plurality of rows and a plurality of columns. The plurality of rows correspond to a plurality of active regions that continuously extend along a first lateral direction, respectively, and the plurality of columns correspond to a plurality of gate structures that discontinuously extend along a second lateral direction, respectively, the first lateral direction and the second lateral direction being perpendicular to each other. A first one of the gate structures comprising a first gap cutting the first gate structure and a second one of the gate structures comprising a second gap cutting the second gate structure are disposed immediately next to each other along the first lateral direction. The first gap and an extension of the second gap are offset from each other along the second lateral direction.

Abstract: A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs. Each of the memory cell includes an inverter (INV3) receiving power from the column selection line, and having its input connected to the word line and its output connected to gates of access transistors. Only the access transistors of a memory cell whose word line and column selection line are simultaneously selected are turned on.

Abstract: A semiconductor memory device includes a plurality of memory cells 205 provided corresponding to nodes of a plurality of word lines (WLBk, WLBk+1) and a plurality of bit line pairs (D1, DB1, D1+1, DB1+1). And column selection lines (S1, S1+1) are provided corresponding to each of the bit line pairs. Each of the memory cell includes an inverter (INV3) receiving power from the column selection line, and having its input connected to the word line and its output connected to gates of access transistors. Only the access transistors of a memory cell whose word line and column selection line are simultaneously selected are turned on.