Patents by Inventor Kazumasa Yanagisawa
Kazumasa Yanagisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8130571Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: June 16, 2011Date of Patent: March 6, 2012Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20120025892Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: ApplicationFiled: October 5, 2011Publication date: February 2, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki MIZUNO, Yusuke KANNO, Kazumasa YANAGISAWA, Yoshihiko YASU, Nobuhiro OODAIRA
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Patent number: 8093723Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.Type: GrantFiled: May 2, 2011Date of Patent: January 10, 2012Assignee: Renesas Electronics CorporationInventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
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Patent number: 8084869Abstract: A technique permitting the reduction in size of a semiconductor device is provided. In a BGA type semiconductor device with a semiconductor chip flip-chip-bonded onto a wiring substrate, bump electrodes of the semiconductor chip are coupled to lands formed at an upper surface of the wiring substrate. The lands at the upper surface of the wiring substrate are coupled electrically to solder balls formed on a lower surface of the wiring substrate. Therefore, the lands include first type lands with lead-out lines coupled thereto and second type lands with lead-out lines not coupled thereto but with vias formed just thereunder. The lands are arrayed in six or more rows at equal pitches in an advancing direction of the rows. However, a row-to-row pitch is not made an equal pitch. In land rows which are likely to cause a short-circuit, the pitch between adjacent rows is made large, while in land rows which are difficult to cause a short-circuit, the pitch between adjacent rows is made small.Type: GrantFiled: June 5, 2009Date of Patent: December 27, 2011Assignee: Renesas Electronics CorporationInventors: Takashi Miwa, Michiaki Sugiyama, Kazumasa Yanagisawa
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Patent number: 8063691Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: GrantFiled: February 3, 2011Date of Patent: November 22, 2011Assignee: Renesas Electronics CorporationInventors: Hiroyuki Mizuno, Yusuke Kanno, Kazumasa Yanagisawa, Yoshihiko Yasu, Nobuhiro Oodaira
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Publication number: 20110246860Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed In an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior In a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: June 16, 2011Publication date: October 6, 2011Inventors: Yutaka SHINAGAWA, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 8031511Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: GrantFiled: February 9, 2011Date of Patent: October 4, 2011Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Publication number: 20110204486Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.Type: ApplicationFiled: May 2, 2011Publication date: August 25, 2011Inventors: Takako FUNAKOSHI, Eiichi MURAKAMI, Kazumasa YANAGISAWA, Kan TAKEUCHI, Hideo AOKI, Hizuru YAMAGUCHI, Takayuki OSHIMA, Kazuyuki TSUNOKUNI, Kousuke OKUYAMA
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Patent number: 7977238Abstract: A manufacturing technique is disclosed for producing a semiconductor integrated circuit device having plural layers of buried wirings, and such that there is prevented the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.Type: GrantFiled: April 21, 2010Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama
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Patent number: 7978545Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: May 6, 2010Date of Patent: July 12, 2011Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Publication number: 20110133827Abstract: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode for shutting off the supply voltage. The conversion circuit is provided with a function for maintaining the potential of an input node of the second circuit block at an operation potential, thereby suppressing a penetrating current flow when the first circuit block is in the second mode. The conversion circuit (MIO1 to MIO4) are commonly used for connecting circuit blocks.Type: ApplicationFiled: February 3, 2011Publication date: June 9, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hiroyuki MIZUNO, Yusuke KANNO, Kazumasa YANAGISAWA, Yoshihiko YASU, Nobuhiro OODAIRA
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Publication number: 20110128780Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: ApplicationFiled: February 9, 2011Publication date: June 2, 2011Inventors: Kenichi OSADA, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Publication number: 20110068826Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.Type: ApplicationFiled: December 1, 2010Publication date: March 24, 2011Inventors: Yuri AZUMA, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Patent number: 7907435Abstract: At the time of, for example, a set operation (SET) for making a phase-change element in a crystalline state, a pulse of a voltage Vreset required for melting the element is applied to the phase-change element, and subsequently a pulse of a voltage Vset that is lower than Vreset and is required for crystallizing the element is applied thereto. And, the magnitude of this voltage Vset is then changed depending on the ambient temperature so that the magnitude of the voltage Vset is small as the temperature becomes high (TH). In this manner, a margin of a write operation between the set operation and a reset operation (RESET) for making the element to be in amorphous state is improved.Type: GrantFiled: September 21, 2005Date of Patent: March 15, 2011Assignee: Renesas Electronics CorporationInventors: Kenichi Osada, Naoki Kitai, Takayuki Kawahara, Kazumasa Yanagisawa
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Publication number: 20110012206Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: ApplicationFiled: September 27, 2010Publication date: January 20, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
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Patent number: 7855593Abstract: A semiconductor integrated circuit device enhanced in design efficiency while achieving multi-functionalization and power saving is to be provided. The semiconductor integrated circuit device has first through third circuit blocks, and is placed in a first power supply state in which the operation of internal circuits in the first circuit block is guaranteed in accordance with an instruction from the third circuit block or a second power supply state in which the operation of the internal circuits is not guaranteed.Type: GrantFiled: July 6, 2009Date of Patent: December 21, 2010Assignee: Renesas Electronics CorporationInventors: Yuri Azuma, Yoshihiko Yasu, Yasuto Igarashi, Takashi Kuraishi, Kazumasa Yanagisawa
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Patent number: 7821824Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: GrantFiled: October 27, 2008Date of Patent: October 26, 2010Assignee: Renesas Electronics CorporationInventors: Yutaka Shinagawa, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7821814Abstract: When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is not operated while storing data is increased. Therefore, there is provided a technique for reducing the leakage current of MOS transistors in SRAM memory cells MC by controlling a potential of a source line ssl of the driver MOS transistors in the memory cells.Type: GrantFiled: August 15, 2008Date of Patent: October 26, 2010Assignee: Renensas Electronics CorporationInventors: Masanao Yamaoka, Kenichi Osada, Kazumasa Yanagisawa
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Publication number: 20100220531Abstract: A semiconductor integrated circuit has a central processing unit and a rewritable nonvolatile memory area disposed in an address space of the central processing unit. The nonvolatile memory area has a first nonvolatile memory area and a second nonvolatile memory area, which memorize information depending on the difference of threshold voltages. The first nonvolatile memory area has the maximum variation width of a threshold voltage for memorizing information set larger than that of the second nonvolatile memory area. When the maximum variation width of the threshold voltage for memorizing information is larger, since stress to a memory cell owing to a rewrite operation of memory information becomes larger, it is inferior in a point of guaranteeing the number of times of rewrite operation; however, since a read current becomes larger, a read speed of memory information can be expedited.Type: ApplicationFiled: May 6, 2010Publication date: September 2, 2010Inventors: YUTAKA SHINAGAWA, Takeshi Kataoka, Eiichi Ishikawa, Toshihiro Tanaka, Kazumasa Yanagisawa, Kazufumi Suzukawa
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Patent number: 7786585Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.Type: GrantFiled: August 8, 2008Date of Patent: August 31, 2010Assignee: Renesas Electronics Corp.Inventors: Takako Funakoshi, Eiichi Murakami, Kazumasa Yanagisawa, Kan Takeuchi, Hideo Aoki, Hizuru Yamaguchi, Takayuki Oshima, Kazuyuki Tsunokuni, Kousuke Okuyama