Patents by Inventor Kazumi Inoh
Kazumi Inoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7696558Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistType: GrantFiled: June 12, 2007Date of Patent: April 13, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Hiroomi Nakajima, Kazumi Inoh
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Patent number: 7301195Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistType: GrantFiled: November 23, 2004Date of Patent: November 27, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Hiroomi Nakajima, Kazumi Inoh
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Publication number: 20070228489Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistType: ApplicationFiled: June 12, 2007Publication date: October 4, 2007Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroomi NAKAJIMA, Kazumi Inoh
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Patent number: 7238988Abstract: A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.Type: GrantFiled: December 1, 2004Date of Patent: July 3, 2007Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Inoh, Takeshi Hamamoto
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Patent number: 7145215Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.Type: GrantFiled: December 22, 2005Date of Patent: December 5, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
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Patent number: 7087475Abstract: A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.Type: GrantFiled: January 4, 2005Date of Patent: August 8, 2006Assignee: Kabushiki Kaisha ToshibaInventor: Kazumi Inoh
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Publication number: 20060157789Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.Type: ApplicationFiled: December 22, 2005Publication date: July 20, 2006Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
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Patent number: 7009273Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.Type: GrantFiled: September 19, 2003Date of Patent: March 7, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
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Publication number: 20050285209Abstract: A silicide film is provided in diffusion regions formed in a semiconductor layer. The silicide film has a thickness substantially same as that of the semiconductor layer. The silicide film has the bottom located in the vicinity of an interface between the insulator film and the semiconductor layer.Type: ApplicationFiled: December 1, 2004Publication date: December 29, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumi Inoh, Takeshi Hamamoto
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Patent number: 6933590Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.Type: GrantFiled: September 3, 2003Date of Patent: August 23, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Atsushi Azuma, Yoshihiro Minami, Hajime Nagano, Hiroaki Yamada, Tatsuya Ohguro, Kenji Kojima, Kazumi Inoh
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Publication number: 20050167751Abstract: A semiconductor memory device comprises a substrate; a semiconductor layer of a first conductive type isolated from the substrate by an insulator layer; a memory transistor having a gate electrode, a drain and a source regions of a second conductive type formed in the semiconductor layer, and a channel body of the first conductive type formed in the semiconductor layer between the regions, the memory transistor operative to store data as a state of majority carriers accumulated in the channel body; an impurity-diffused region of the first conductive type formed at a location in contact with the upper surface of the drain region, the impurity-diffused region having a higher impurity concentration of the first conductive type than an impurity concentration of the second conductive type in the drain region; and a write transistor including a bipolar transistor having the impurity-diffused region as an emitter region, the drain region as a base region and the channel body as a collector region, the write transistType: ApplicationFiled: November 23, 2004Publication date: August 4, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroomi Nakajima, Kazumi Inoh
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Publication number: 20050158933Abstract: A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.Type: ApplicationFiled: January 4, 2005Publication date: July 21, 2005Inventor: Kazumi Inoh
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Patent number: 6855969Abstract: A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.Type: GrantFiled: May 29, 2002Date of Patent: February 15, 2005Assignee: Kabushiki Kaisha ToshibaInventor: Kazumi Inoh
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Publication number: 20040222471Abstract: A semiconductor device includes first and second gate electrode, first and second gate insulating film, semiconductor layer, source and drain regions, and source and drain electrodes. The first gate electrode is formed in the insulating film. The first gate insulating film is formed on the first gate electrode. The semiconductor layer is formed on the insulating film. The source and drain regions are formed in the semiconductor layer. The source and drain electrodes are respectively formed on the source and drain regions. The positions of side wall surfaces of the source and drain electrodes which face each other are substantially aligned with the positions of both side wall surfaces of the first gate electrode in a direction perpendicular to the surface of the insulating film. The second gate insulating film is formed on the semiconductor layer. The second gate electrode is formed on the second gate insulating film.Type: ApplicationFiled: May 29, 2002Publication date: November 11, 2004Inventor: Kazumi Inoh
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Publication number: 20040129998Abstract: A semiconductor device includes a semiconductor substrate, cavities, and an element isolating region. The cavities, which are each shaped like a flat plate, are made in the semiconductor substrate. The element isolating region is formed in the surface of the semiconductor substrate and located at the sides of the cavities.Type: ApplicationFiled: September 19, 2003Publication date: July 8, 2004Inventors: Kazumi Inoh, Hidemi Ishiuchi, Satoshi Matsuda, Ichiro Mizushima, Tsutomu Sato
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Publication number: 20040113228Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.Type: ApplicationFiled: September 3, 2003Publication date: June 17, 2004Inventors: Takashi Yamada, Atsushi Azuma, Yoshihiro Minami, Hajime Nagano, Hiroaki Yamada, Tatsuya Ohguro, Kenji Kojima, Kazumi Inoh
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Patent number: 6635952Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.Type: GrantFiled: March 27, 2002Date of Patent: October 21, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Kazumi Inoh, Shigeru Kawanaka, Yoshihiro Minami, Yasuhiro Katsumata
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Publication number: 20020140115Abstract: A semiconductor device comprises: a semiconductor substrate; an insulating layer provided on said semiconductor substrate; a first semiconductor layer provided on said insulating layer; a plurality of openings penetrating said first semiconductor layer and said insulating layer and reaching said semiconductor substrate; and second semiconductor layers filling said openings by selective growth and connected to said semiconductor substrate, wherein areal sizes of said plurality of openings are substantially equal to each other.Type: ApplicationFiled: March 27, 2002Publication date: October 3, 2002Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Kazumi Inoh, Shigeru Kawanaka, Yoshihiro Minami, Yasuhiro Katsumata
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Patent number: 6376897Abstract: In a bipolar transistor improved to exhibit an excellent high-frequency property by decreasing the width of the intrinsic base with without increasing the base resistance, an emitter region, intrinsic base region and collector region are closely aligned on an insulating layer, and the intrinsic base region and the collector region make a protrusion projecting upward from the substrate surface. The protrusion has a width wider than the width of the intrinsic base region.Type: GrantFiled: May 19, 1999Date of Patent: April 23, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Yamada, Hideaki Nii, Makoto Yoshimi, Tomoaki Shino, Kazumi Inoh, Shigeru Kawanaka, Tsuneaki Fuse, Sadayuki Yoshitomi
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Patent number: 6174779Abstract: In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.Type: GrantFiled: March 15, 1999Date of Patent: January 16, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Tomoaki Shino, Takashi Yamada, Makoto Yoshimi, Shigeru Kawanaka, Hideaki Nii, Kazumi Inoh, Tsuneaki Fuse, Sadayuki Yoshitomi, Mamoru Terauchi