Abstract: A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate.

Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.

Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.

Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.