Patents by Inventor Kazunari Ishimaru

Kazunari Ishimaru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5960272
    Abstract: The present invention is to provide a semiconductor integrated circuit having bipolar transistor elements with a reduced isolating distance between adjacent transistors and a reduced collector/substrate capacitance. In the surface of a P-type semiconductor substrate, N.sup.+ type regions are formed serving as buried collector regions of bipolar transistors TR1 and TR2. Between the N.sup.+ type regions, a P-type region for element isolation is provided not in contact with the N.sup.+ type regions. A P-type impurity concentration in the peripheral portions of N.sup.+ type regions is equal to that of the semiconductor substrate. The insulating film serving as an element-isolating layer is provided on the P-type region in contact therewith and thus electrically isolates adjacent bipolar transistors.
    Type: Grant
    Filed: October 15, 1996
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5886387
    Abstract: Disclosed are a semiconductor integrated circuit device capable of including both a bipolar transistor and a MOS transistor while maintaining high performances of then both and a method of fabricating the device. On a p-type silicon substrate a plurality of n.sup.+ -type regions are formed below the buried collector region of a bipolar transistor and the n-type well region of a MOS transistor. A plurality of p-type regions are formed below the isolation region of the bipolar transistor and the p-type well region of the MOS transistor. An epitaxial layer is formed on the substrate including these n.sup.+ -type and p-type regions. This epitaxial layer forms element region layers having a bipolar transistor region and a MOS transistor region. The thickness of the layer of the bipolar transistor region is smaller than that of the layer of the MOS transistor region.
    Type: Grant
    Filed: September 23, 1996
    Date of Patent: March 23, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahito Nishigohri, Kazunari Ishimaru
  • Patent number: 5731623
    Abstract: A buried collector layer is formed on a semiconductor substrate. An epitaxial layer is formed on the burled collector layer. A plurality of element separating trenches of roughly the same depth and filled with an insulating material are formed in the epitaxial layer. When these trenches are formed deep enough to penetrate the buried collector layer to the semiconductor substrate, an impurity region of conductivity the same as that of the buried collector layer is formed at a predetermined position of the semiconductor substrate and adjoining to at least one bottom portion of a plurality of the trenches. Further, when a separation layer is formed on the semiconductor substrate and adjoining to the buried collector layer to separate the semiconductor device from another adjacent semiconductor device, at least one of a plurality of trenches is formed on a boundary surface between the buried collector layer and the separation layer.
    Type: Grant
    Filed: April 25, 1997
    Date of Patent: March 24, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5578518
    Abstract: A semiconductor device comprises a semiconductor substrate having a major surface, a trench device isolation region having a trench selectively formed to define at least one island region in the major surface of the semiconductor substrate and a filler insulatively formed within the trench, an elongated gate electrode insulatively formed over a central portion of the island region so that each of its both ends which are opposed to each other in the direction of its length overlaps the trench device isolation region, and source and drain regions formed within the island region on the both sides of the gate electrode. The surface of the trench device isolation region is formed lower than the major surface of the semiconductor substrate.
    Type: Grant
    Filed: December 15, 1994
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidetoshi Koike, Kazunari Ishimaru, Hiroshi Gojohbori, Fumitomo Matsuoka
  • Patent number: 5518961
    Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.
    Type: Grant
    Filed: October 5, 1994
    Date of Patent: May 21, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5496744
    Abstract: In a method of manufacturing a bipolar transistor by forming emitter regions of PNP and NPN transistors with diffusion of impurity from the polycrystalline silicon film into the substrate, the B-doped polycrystalline silicon film is deposited on the interlayer insulating film in which the emitter holes of the PNP and NPN transistors are made. Further, the interlayer insulating film is deposited on this film, and the portion of the insulating film which situated on the NPN transistor region is removed. Then, the thermal treatment is carried out in a high-concentration P atmosphere, so as to change the portion of the film which is located on the NPN transistor region to a P-doped polycrystalline silicon film. With this thermal treatment, the P-type and N-type emitter diffusion regions are formed on the base regions of the PNP and NPN transistors.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: March 5, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru
  • Patent number: 5397910
    Abstract: In a semiconductor device of gate self-alignment structure, at least two lamination layer portions each composed of a gate electrode, an insulating film and a conductive film are formed on a semiconductor substrate with a contact hole sandwiched therebetween. A wire is formed on the respective lamination layer portions. Further, a total thickness of the conductive film and the wire is determined to be large enough to prevent impurities implanted into the wire from being doped into the gate electrode. In formation of the gate self-alignment structure, an insulating side wall is formed on the side wall of the contact hole, to insulate the gate electrode from the wire or vice versa.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: March 14, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazunari Ishimaru