Patents by Inventor Kazuo Kameya

Kazuo Kameya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5389902
    Abstract: The size of the electromagnetic delay line is reduced by arranging chip capacitors in two rows in a staggered relationship along the lengthwise direction of a base board so that the overall length can be substantially reduced as compared to the conventional structure in which the chip capacitors are arranged in a single row. In particular, the height of the profile of the package for the electromagnetic delay line can be substantially reduced as compared to the comparable conventional ones. Furthermore, this electromagnetic delay line can cover a wide range of delay time while maintaining a same size and configuration, and offers stable and desirable properties. The present invention also offers an electric advantage in that the bridging capacitance is produced while the parallel capacitance is reduced. This contributes to the improvement in the performance of the electromagnetic delay line.
    Type: Grant
    Filed: November 9, 1993
    Date of Patent: February 14, 1995
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5331298
    Abstract: A lumped constant type electromagnetic delay line employs an inductive device consisting of a plurality of turns of electroconductive wire in combination with chip capacitors connected to a plurality of taps provided in the inductive device so as to form a ladder circuit consisting of a plurality of delay circuit sections. The coil wire ends and the taps of the inductive device of the present invention are all twisted and extended in the same direction, and are all provided with a uniform and sufficient rigidity. Therefore, the process of connecting these taps and coil wire ends to the corresponding electrodes is simplified, and is therefore made better adapted for automatization. During the process of manufacture, a series of inductive devices can be fabricated as a continuous process of winding a coil wire around an elongated bobbin, and all the taps and coil wire ends are laterally extended and twisted in the same manner so that the entire process is significantly simplified.
    Type: Grant
    Filed: January 12, 1993
    Date of Patent: July 19, 1994
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5053730
    Abstract: By appropriately determining the dimensions and positional relationships of the terminal pieces of an electronic component such as an electromagnetic delay line, the terminal pieces are capable of conducting super high speed signals without unduly attenuating or reflecting them. A signal terminal piece and a ground terminal piece situated in a common plane so as to define a gap G filled with dielectric material therebetween form an impedance line having a desired characteristic impedance. By selecting the gap from a range between 0.1 mm and 0.6 mm, it is possible to obtain a normally desired characteristic impedance when the dimensions of the terminal pieces and related parts are set to practical values. When a pair of ground terminal pieces are arranged on either side of a signal terminal piece, each of the gaps may be selected from a range between 0.1 mm and 1.0 mm when the gaps are air gaps, and from a range between 0.2 mm and 1.5 mm when the gaps are filled with dielectric material such as epoxy resin.
    Type: Grant
    Filed: July 20, 1990
    Date of Patent: October 1, 1991
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5049707
    Abstract: A switching device for super high frequency ranges comprising a common fixed contact and a pair of selectable fixed contacts, and moveble contacts which are slidable over them so as to selectively and electrically connect the common fixed contact to one of the selectable fixed contacts. A pair of buffer electrodes are placed between the common fixed contact and the selectable fixed contacts to reduce the electrostatic capacitance between the fixed contacts and reduce signal attenuation in super high frequency ranges. The buffer electrodes are electrically isolated without being connected to any external circuit and thereby reduce electrical capacitance produced between the common fixed contact and the selectable fixed contacts without creating excessive gaps therebetween. Such gaps would prevent smooth sliding movement of the moveable contacts.
    Type: Grant
    Filed: August 15, 1990
    Date of Patent: September 17, 1991
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 5030932
    Abstract: This electromagnetic delay line is formed by disposing a ground electrode on one surface of a thin dielectric layer and serially connecting main electroconductive strips which are arranged in parallel at certain intervals on the opposite surface of the dielectric layer to form a zigzag strip to face the ground electrode and further, each main electroconductive strip itself is folded to be configured. Accordingly, the negative coupling produced in the zigzag strip is decreased and dispersed as well, thus improving the delay characteristics for the ultra-high frequency signal.
    Type: Grant
    Filed: July 5, 1989
    Date of Patent: July 9, 1991
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4829272
    Abstract: An electromagnetic variable delay line system in which the change in the output impedance of the delay line as its delay time is varied is compensated by an electronic device such as a field effect transistor which is connected across the output end of the variable delay line system. Therefore, generation of undesirable reflected waves can be prevented and high speed signals can be processed without distorting the signals.
    Type: Grant
    Filed: June 10, 1988
    Date of Patent: May 9, 1989
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4821003
    Abstract: This electromagnetic variable delay line includes: a delay line, which includes an inductance device and at least one variable capacitance diode connected thereto, and possessing a non linear operational property; and a circuit device for supplying an output control signal to the variable capacitance diode in a manner which varies non linearly with an input control signal. The circuit means has a non linear property which is substantially complementary and opposite to the non linear delay property of the delay line. Optionally but desirably, the delay line may include: several delay line elments, connected in series, each of which includes an inductance device and a variable capacitance diode connected to the inductance device, the variable capacitance diodes being connected together; and buffer circuits connecting together each adjacent pair of these delay line elements.
    Type: Grant
    Filed: December 30, 1987
    Date of Patent: April 11, 1989
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4758807
    Abstract: This distributed constant type electromagnetic delay line has an elongated bobbin which includes, laminated together, a substantially rectangular dielectric layer and a substantially rectangular ground plane, and further includes an electroconductive strip, constituted by a single layer solenoid fixedly secured to the bobbin by its outer surface. As a variation, this distributed constant type electromagnetic delay line may have an elongated bobbin which includes, laminated together: a first substantially rectangular dielectric layer; a second substantially rectangular dielectric layer; and a substantially rectangular ground plane sandwiched between the first and second dielectric layers; and may further include an electroconductive strip, constituted by a single layer solenoid fixedly secured to the bobbin and wound in a spaced manner around the outer surface of the bobbin confronting the ground plane.
    Type: Grant
    Filed: December 17, 1985
    Date of Patent: July 19, 1988
    Assignee: Elmec Corporation
    Inventors: Kazuo Kameya, Tsuyoshi Suaa
  • Patent number: 4701723
    Abstract: This connection construction for an electronic component includes a circuit board, a circuit pattern on the circuit board, an external connection terminal mounted to the circuit board and connected to the circuit pattern, a ground electrode opposing the external connection terminal, and a mass of dielectric material interposed between the ground electrode and the external connection terminal. Thereby proper connection is obtained for the circuit board, without introducing any undesirable delay, or deterioration or degradation of output signal therefrom. Thus, a connection construction for an electronic component is obtained which is particularly suitable for handling high speed signals.
    Type: Grant
    Filed: February 5, 1986
    Date of Patent: October 20, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4697162
    Abstract: This variable delay line system includes a variable delay line which has two output ends and a plurality of signal input points at its intermediate points, a means for selecting one of the input points of the variable delay line and for inputting a signal thereto, and a means for switching the signals from the output ends of the variable delay line and for outputting them. Optionally, a fixed delay line can further be included. Thereby, the varibale delay line system has a simple and compact structure and is effective.
    Type: Grant
    Filed: February 5, 1986
    Date of Patent: September 29, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4695812
    Abstract: This distributed constant type delay line has an inductance element which has a plurality of main portions lying generally in parallel stacked planes. Each of the main portions has a conducting portion with a generally central line, the conducting portions being connected in series with one another with their the central lines lying generally parallel to one another and being alternately staggered to and fro in the direction generally perpendicular to them and generally parallel to the stacked planes. A ground electrode is interposed between the conducting portions of two neighboring ones of the main portions of the inductance element. And a dielectric layer is interposed between the ground electrode and a neighboring one of the main portions of the inductance element. Thereby, a very efficient and compact construction becomes available, which is suitable for being made as a chip. Optionally, capacitance compensating electrodes are defined as extending out from the main portions of the inductance element.
    Type: Grant
    Filed: March 14, 1986
    Date of Patent: September 22, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4686495
    Abstract: This finely variable delay line includes a first variable delay line element the delay time provided by which can be relatively coarsely varied, and a second variable delay line element the delay time provided by which can be relatively finely varied, connected in series with the first variable delay line. A reflection circuit is constituted between an element included in the second variable delay line and another element of the construction, the reflection circuit reflecting back a signal towards the element of the second variable delay line. Although some slight mismatching is in fact present, such mismatching is quite negligible in practice, and this variable delay line can be very finely adjusted by steps of as little as 0.5% of its total range or less.
    Type: Grant
    Filed: February 19, 1986
    Date of Patent: August 11, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4656443
    Abstract: This variable delay line makes use of a transmission line as a delay line element and is suitable for switching over the delay time of a high speed signal having for instance a rise time of one nanosecond or less. And this variable delay line includes a transmission line which includes an electroconductive path and a ground plate disposed opposingly with a dielectric body interposed therebetween, a fixed contact array consisting of fixed contacts provided at certain intervals along the electroconductive path, and a movable contact which may be slid along contacting the fixed contacts of the fixed contact array. Particularly, the movable contact contacts one of the fixed contacts in the fixed contact array in a first state and contacts two neighboring ones of the fixed contacts in the fixed contact array in a second state, and the movable contact may be slid over the fixed contact array by alternatingly repeating the first and the second states.
    Type: Grant
    Filed: January 10, 1985
    Date of Patent: April 7, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4649356
    Abstract: A low profile high speed electromagnetic delay line capable of long delay times and transmitting signals having rise times less than approximately one nanosecond is described. The electromagnetic delay line is of a single in-line package configuration, but of such a configuration that commercial production is facilitated. A coil assembly has input and output and intermediate terminals extending from the same side of the coil assembly to be connected to flat electrodes on an insulating plate. These connections all occur on the same edge of the insulating plate. At a second opposed edge of the insulating plate are connected terminals leading to external circuits. The various electrodes which receive the coil connections are also connected to the individual capacitors of an elongated flat plate capacitor, and these electrodes are in turn connected to the external connections.
    Type: Grant
    Filed: January 2, 1986
    Date of Patent: March 10, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4642588
    Abstract: This invention aims to provide a method of adjustment for a variable delay line which is provided with two delay line elements of dissimilar delay times and switch means capable of selectively switching from one to the other of the two delay line elements and adapted to enable the delay time to be digitally increased or decreased by the delay time difference produced by the selective switching between the delay time elements. This method allows the delay time to be finely adjusted with high accuracy of the order of 1 to some tens of ps by changing the delay time of either of the two delay line elements which has a smaller delay time than the other.
    Type: Grant
    Filed: May 22, 1984
    Date of Patent: February 10, 1987
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4620164
    Abstract: A variable delay line using a lumped constant type electromagnetic delay line and enjoying a superhigh-speed rising characteristic is disclosed, which comprises an inductance element formed by winding a conductor and possessed of a plurality of taps, a plurality of capacitors having electrodes thereof on one side kept in common connection, a plurality of linking electrodes disposed along the inductance element and adapted to interconnect the taps of the inductance element and the electrodes of the capacitors on the other side, fixed contacts formed of limited surface regions of the linking electrodes, and movable contact means adapted to advance on the fixed contacts while keeping pressed contact with each fixed contact so as to permit selection of the taps of the inductance element.
    Type: Grant
    Filed: October 30, 1984
    Date of Patent: October 28, 1986
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4583062
    Abstract: An electromagnetic delay line is disclosed which is provided with an inductance element formed by a conductor winding with capacitors arranged between the inductance element and ground dividing the element into a plurality of sections. These sections are formed of loops resulting from the winding of the conductor and the loops of adjacent sections are formed in opposed planes divergent in alternately opposite directions. The electromagnetic delay line acquires the optimum coupling coefficient between the sections and achieves advantageous delay characteristics in a wide frequency band including the ultra-high frequency band. Particularly, it obtains the ultra-high speed rise time of less than 1 ns.
    Type: Grant
    Filed: January 31, 1984
    Date of Patent: April 15, 1986
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4570136
    Abstract: An electromagnetic delay line of a distributed constant type making use of a zigzag strip as a strip line and suitable for use in very high frequency ranges. The zigzag strip comprises electroconductive strips which are bent in such a manner that they are arranged on a first imaginary plane and a second imaginary plane parallel and opposite thereto and spaced apart therefrom by an interval of T, in an alternating manner, and the pitch P and the interval T are so related to each other that the ratio T/P is greater than zero and smaller than unity. Therefore the coupling produced in the zigzag strip is enhanced and the enhanced positive coupling controls negative coupling by reducing or canceling it.
    Type: Grant
    Filed: December 26, 1984
    Date of Patent: February 11, 1986
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4570135
    Abstract: An ultra-high speed lumped constant delay line includes an inductance element formed by winding a conductor into a single layer solenoid shape of predescribed pitch P, and a plurality of capacitors connected between ground and the conductor at every turn of the inductance element. The pitch P and the winding diameter T in the direction of short diameter are set according to the relation 0.2<P/T<1.9.
    Type: Grant
    Filed: February 18, 1983
    Date of Patent: February 11, 1986
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya
  • Patent number: 4565981
    Abstract: An electromagnetic delay line of novel construction is disclosed which comprises an inductance element having a conductor wound as regularly spaced in the form of a single-layer solenoid and a plurality of capacitors inserted to connect the conductor of the inductance element and a ground after a ladder network. The construction is characterized in that the capacitors are connected one each to a plurality of points per turn of the conductor so as to give rise to a plurality of sections for each turn of the conductor. The electromagnetic delay line thus constructed, therefore, is very compact and exhibits a very quick rise of not more than 1 ns.
    Type: Grant
    Filed: September 21, 1984
    Date of Patent: January 21, 1986
    Assignee: Elmec Corporation
    Inventor: Kazuo Kameya