Patents by Inventor Kazuo Kanetani
Kazuo Kanetani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7685455Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.Type: GrantFiled: November 7, 2007Date of Patent: March 23, 2010Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroaki Nambu, Masao Shinozaki, Kazuo Kanetani, Hideto Kazama
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Publication number: 20080072095Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.Type: ApplicationFiled: November 7, 2007Publication date: March 20, 2008Inventors: Hiroaki Nambu, Masao Shinozaki, Kazuo Kanetani, Hideto Kazama
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Patent number: 7296173Abstract: A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.Type: GrantFiled: February 2, 2004Date of Patent: November 13, 2007Assignees: Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd.Inventors: Hiroaki Nambu, Masao Shinozaki, Kazuo Kanetani, Hideto Kazama
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Publication number: 20070236844Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: June 6, 2007Publication date: October 11, 2007Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 7233045Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: GrantFiled: October 12, 2004Date of Patent: June 19, 2007Assignee: Hitachi LtdInventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 6998878Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.Type: GrantFiled: January 12, 2004Date of Patent: February 14, 2006Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Patent number: 6954401Abstract: It is an object of the invention to provide a circuit configuration wherein a decoder control signal ?2 is rendered unnecessary between an address buffer control signal ?1 and the decoder control signal ?2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.Type: GrantFiled: December 29, 2004Date of Patent: October 11, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu
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Publication number: 20050111265Abstract: It is an object of the invention to provide a circuit configuration wherein a decoder control signal ?2 is rendered unnecessary between an address buffer control signal ?1 and the decoder control signal ?2, thereby implementing speed-up in operation of a decoder circuit. The object is attained by adoption of a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.Type: ApplicationFiled: December 29, 2004Publication date: May 26, 2005Inventors: Kazuo Kanetani, Hiroaki Nambu
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Publication number: 20050063112Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: October 12, 2004Publication date: March 24, 2005Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 6842394Abstract: A high-speed, reduced power consumption address decoder circuit, wherein a decoder control signal ?2 is rendered unnecessary between an address buffer control signal?1 and the decoder control signal ?2, thereby implementing speed-up in operation of a decoder circuit. Improved speed and reduced power consumption are attained by a configuration wherein a buffer is integrated with a decoder, so that an output current path of transistors making up the address buffer, and that of transistors making up the decoder are connected with each other in series, thereby forming an output current path of decoder output. With the invention, speed-up in operation, lower power consumption, and higher cycle, of decoder circuits, can be achieved. Further, in the case of using the decoder circuits in a semiconductor memory, it is possible to achieve shortening of access time, lower power consumption, and higher cycle with reference to the semiconductor memory.Type: GrantFiled: October 2, 2002Date of Patent: January 11, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu
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Patent number: 6826109Abstract: The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.Type: GrantFiled: January 16, 2003Date of Patent: November 30, 2004Assignee: Hitachi, Ltd.Inventors: Shigeru Nakahara, Satoshi Iwahashi, Takeshi Suzuki, Keiichi Higeta, Kazuo Kanetani
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Patent number: 6806516Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: GrantFiled: February 21, 2003Date of Patent: October 19, 2004Assignee: Renesas Technology Corp.Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 6807115Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: GrantFiled: February 10, 2003Date of Patent: October 19, 2004Assignees: Renesas Technology Corporation, Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20040183582Abstract: The present invention provides a semiconductor integrated circuit in which a timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated and the data signal is fetched synchronously with the internal clock signal.Type: ApplicationFiled: February 2, 2004Publication date: September 23, 2004Inventors: Hiroaki Nambu, Masao Shinozaki, Kazuo Kanetani, Hideto Kazama
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Publication number: 20040169527Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced.Type: ApplicationFiled: January 12, 2004Publication date: September 2, 2004Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Patent number: 6677782Abstract: To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit is composed by a semiconductor logic circuit wherein the number of columns of transistors for pulling down at an output node is small even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. According to the present invention, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and in a semiconductor memory for example, the reduction of access time and power consumption and the increase of the cycles are enabled.Type: GrantFiled: April 24, 2001Date of Patent: January 13, 2004Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Takeshi Kusunoki, Keiichi Higeta, Kunihiko Yamaguchi, Fumihiko Arakawa
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Publication number: 20030222285Abstract: Disclosed herewith is a semiconductor device improved to prevent withstand voltage defects that might occur in each MOSFET used therein and a system to be designed easily and prevented from withstand voltage defects that might occur in each semiconductor used therein. The system includes the first and second input circuits, each being constituted by MOSFETs manufactured in the same process. The first input circuit receives a voltage of a first signal inputted from a first external terminal and divided by first and second resistor means while the AC component of the input signal is transmitted to the input circuit through a capacitor disposed in parallel to the first resistor means. The second input circuit receives a second input signal inputted from a second external terminal and reduced in signal amplitude so as to become smaller than that of the first input signal.Type: ApplicationFiled: February 21, 2003Publication date: December 4, 2003Applicant: Hitachi, Ltd.Inventors: Takemi Negishi, Hiroaki Nambu, Kazuo Kanetani, Hideto Kazama
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Patent number: 6617610Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: GrantFiled: December 13, 2001Date of Patent: September 9, 2003Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta
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Publication number: 20030142526Abstract: The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.Type: ApplicationFiled: January 16, 2003Publication date: July 31, 2003Applicant: Hitachi, Ltd.Inventors: Shigeru Nakahara, Satoshi Iwahashi, Takeshi Suzuki, Keiichi Higeta, Kazuo Kanetani
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Publication number: 20030123309Abstract: In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.Type: ApplicationFiled: February 10, 2003Publication date: July 3, 2003Applicant: Hitachi, Ltd.Inventors: Kazuo Kanetani, Hiroaki Nambu, Kaname Yamasaki, Fumihiko Arakawa, Takeshi Kusunoki, Keiichi Higeta