Abstract: An exhaust heat recovery device for an engine including a Rankine cycle, including a steam accumulator that stores a surplus of a working medium for driving a turbine, and a leveling line that discharges the stored surplus working medium from the steam accumulator to the turbine, when the turbine cannot output predetermined power only with the working medium flowing out from a boiler, and levels the power outputted from the turbine. Since the power outputted from the turbine can be leveled without reduction of the power, even if the working medium cannot vaporize with the boiler immediately after start-up, immediately before stop, or during a low-load operation of the engine, exhaust heat from the engine can be efficiently used.

Abstract: A jig used for repairing a component having a tang with a hole is comprised of: a main body defining a standard line; a positioning pin detachably attached to the main body and so dimensioned as to fit in the hole to make an axial center of the hole be aligned with the standard line; and a clamp so structured as to catch hold of the tang to secure the component to the main body in a state where the axial center is aligned with the standard line.

Abstract: An exhaust heat recovery device for an engine including a Rankine cycle, including a steam accumulator that stores a surplus of a working medium for driving a turbine, and a leveling line that discharges the stored surplus working medium from the steam accumulator to the turbine, when the turbine cannot output predetermined power only with the working medium flowing out from a boiler, and levels the power outputted from the turbine. Since the power outputted from the turbine can be leveled without reduction of the power, even if the working medium cannot vaporize with the boiler immediately after start-up, immediately before stop, or during a low-load operation of the engine, exhaust heat from the engine can be efficiently used.

Abstract: A jig used for repairing a component having a tang with a hole is comprised of: a main body defining a standard line; a positioning pin detachably attached to the main body and so dimensioned as to fit in the hole to make an axial center of the hole be aligned with the standard line; and a clamp so structured as to catch hold of the tang to secure the component to the main body in a state where the axial center is aligned with the standard line.

Abstract: A receiver input circuit comprises an R-? type low-pass filter, a small-capacitance type coupling capacitor element and a parallel tuning circuit. The low-pass filter has an inductor element and a first capacitor element both connected in series, and a shunt-connected second capacitor element. The first and second capacitor elements are equivalent to ones obtained by dividing a normal shunt-connected capacitor element into two. A total capacitance value thereof is selected equal to the capacitance value of the normal shunt-connected capacitor element. The parallel tuning circuit makes use of a tuning first variable capacitance type capacitor element. A second variable capacitance type capacitor element is used for the small-capacitance type coupling capacitor element.

Abstract: With the objective of providing a scanning receiver capable of capturing a target radio wave in an extremely short period of time by use of a simple constituting means, a plurality of wide frequency division bands in which a full frequency range is divided into predetermined frequency ranges are set and the field intensities of received radio waves are retrieved using the output of an intermediate frequency amplifier circuit over the set wide frequency division bands in order. Further, when a received radio wave having a field intensity greater than or equal to a prescribed level is obtained upon the above retrieval, receive frequencies are swept from one end of each of the wide frequency division bands to the other end thereof. When a target radio wave can be captured upon the above sweeping, transition to the operation of receiving the target radio wave is performed.

Abstract: The present invention provides a phase comparison signal processing circuit which processes an output rectangular wave signal of a digital phase comparator of a PLL, expands a pullable-in frequency width of the PLL and shortens a synchronization time. The phase comparison signal processing circuit includes a first signal path which is parallel-connected between a voltage shifter for converting a rectangular wave signal to a bipolar signal and an output terminal and comprises a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and a common addition circuit, a second signal path comprising a rectifying circuit, an integration holding circuit, a differentiation circuit, a gate circuit, a voltage hold circuit and the addition circuit, and a control signal generator for individually controlling the integration holding circuits and the gate circuits of the first and second signal paths.

Abstract: The present invention provides a voltage controlled oscillator capable of obtaining an oscillation signal having a relatively low frequency with a simple circuit configuration without using AGC means and a semiconductor internal resistor. The voltage controlled oscillator includes a switching circuit which inputs therein a frequency control voltage and its inverse frequency control voltage and selects and outputs the frequency control voltage or the inverse frequency control voltage in response to an output logic state of a switching voltage generating section, and an integration circuit which integrates the output voltage of the switching circuit to form a triangular wave signal.

Abstract: The present invention provides an active inductor comprising an input terminal, a primary all-pass type 90° phase-delayed stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-delayed stage, a 90° phase-delayed signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-delayed stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal.

Abstract: The present invention provides an active capacitor comprising an input terminal, a primary all-pass type 90° phase-advanced stage constituted of discrete elements, and a phase inversion amplifying stage and including a constitution in which a signal supplied to the input terminal is inputted to the primary all-pass type 90° phase-advanced stage, a 90° phase-advanced signal obtained at its output is inputted to the phase inversion amplifying stage subsequent to the primary all-pass type 90° phase-advanced stage and phase-inversion amplified thereat, and an output produced from the phase inversion amplifying stage is feedback-coupled to the input terminal.

Abstract: The present invention provides an active capacitor that includes an active all-pass type 90° phase delaying circuit comprising an operational amplifier, a first resistor connected between an inversion input end of the operational amplifier and an input terminal, a second resistor connected between a non-inversion input end of the operational amplifier and the input terminal, a third resistor connected between an output end of the operational amplifier and the non-inversion input end, and a capacitor connected between the non-inversion input end and a ground point; and a fourth resistor having a resistance value sufficiently lower than respective resistance values of the first through third resistors connected between input and output terminals of the active all-pass type 90° phase delaying circuit and an impedance value of the capacitor. Thus, an equivalent capacitor is obtained between the input terminal and the ground point.

Abstract: The present invention provides a receiver input circuit capable of maintaining impedance matching with an antenna feeder wire within all frequency bands to be used and constituting parallel resonant circuits in multi-stage form without using additional circuit portions. The receiver input circuit includes a constant resistance branching filter, a coupling inductor and a tuning circuit. The constant resistance branching filter comprises a low-pass filter and a high-pass filter having termination resistors connected thereto. The low-pass filter and the high-pass filter respectively have equal cut-off frequencies selected to frequencies slightly lower than those lying in a used frequency band and include input ends connected in common to an input terminal of the constant resistance branching filter connected to the antenna feeder wire. The tuning circuit has a parallel resonant circuit constituted of a tuning inductor and a variable capacitance diode.

Abstract: The present invention provides an active inductor that includes an active all-pass type 90° phase advancing circuit comprising an operational amplifier, a first resistor connected between an inversion input end of the operational amplifier and an input terminal, a capacitor connected between a non-inversion input end of the operational amplifier and the input terminal, a second resistor connected between an output end of the operational amplifier and the non-inversion input end, and a third resistor connected between the non-inversion input end and a ground point; and a fourth resistor having a resistance value sufficiently lower than respective resistance values of the first through third resistors connected between input and output terminals of the active all-pass type 90° phase advancing circuit and an impedance value of the capacitor. Thus, an equivalent inductor is obtained between the input terminal and the ground point.

Abstract: A receiver input circuit comprises an R-? type low-pass filter, a small-capacitance type coupling capacitor element and a parallel tuning circuit. The low-pass filter has an inductor element and a first capacitor element both connected in series, and a shunt-connected second capacitor element. The first and second capacitor elements are equivalent to ones obtained by dividing a normal shunt-connected capacitor element into two. A total capacitance value thereof is selected equal to the capacitance value of the normal shunt-connected capacitor element. The parallel tuning circuit makes use of a tuning first variable capacitance type capacitor element. A second variable capacitance type capacitor element is used for the small-capacitance type coupling capacitor element.

Abstract: A non-linear circuit includes a non-linear basic circuit which is provided with an op amplifier, negative feedback circuits thereof, a positive feedback circuit thereof, an input resistor and a second input resistor and transforms an input control voltage into a non-linear basic control voltage; a weighting circuit which includes voltage division resistors and divides the input control voltage; an offset voltage applying circuit which includes an offset voltage source and generates an offset voltage; and an adding circuit which includes a second op amplifier, negative feedback circuits thereof and third, fourth and fifth input resistors thereof and which adds the non-linear basic control voltage, division control voltage and offset voltage together and outputs the result of addition thereof. A controlled load circuit including a non-linear element is connected to the output of the second op amplifier.

Abstract: A variable resistance circuit includes a PIN diode circuit which adjusts an RF resistance for PIN diodes according to a control voltage, a first means which level-shifts one control voltage by a level shift circuit and applies a non-linear characteristic to the so level-shifted control voltage using a zener diode characteristic by a zener diode circuit, a second means which applies a voltage offset to the other control voltage by a weighting circuit, and an adding circuit which adds respective output voltages of the first means and the second means. When the output of the adding circuit is applied to the PIN diode circuit, the shift voltage of the level shift circuit, the zener characteristic of the zener diode circuit and the voltage offset of the weighting circuit are selected and adjusted to set the value of the RF resistance of the PIN diode circuit so as to change substantially linearly with respect to a change in control voltage.

Abstract: An air deflector (10) is attached to a roof of a cab (2). A rear edge portion (12) of the air deflector has a configuration identical with an upper part of a vertical front face (4) of a van body (3) or a configuration closely resembling the upper part thereof, as viewed from the front. A marker lamp (40) is located on a ridge portion (32) of the air deflector in proximity to the rear edge portion. An upper surface (41) and a side surface (43) of the marker lamp are formed to continue an upper face (31) and a side face (33) of the air deflector, and a ridge portion (42) of the marker lamp is in alignment with the ridge portion of the air deflector. The air deflector can ensure visibility of the marker lamps, while preventing the flow of air from impinging on the upper corner areas of the front face of the van body, whereby the aerodynamic performance of the vehicle is improved.

Abstract: An FSK signal generator includes a first clock generator which generates a first clock pulse having a frequency n·f1, a second clock generator which generates a second clock pulse having a frequency n·f2, a switch which serves so as to output the first or second clock pulse in accordance with input data codes, a counter which outputs each address code according to the count of the outputted clock pulse, a read-only memory in which coded values of respective sampling points of a signal waveform lying in one cycle are written in address order and from which the coded values of the respective sampling points are read in response to the address codes of the counter, a digital/analog converter which converts the read coded values into an analog signal, and a low-pass filter which smoothes the analog signal to form an FSK signal.

Abstract: In demodulation of a FSK signal, a circuit for detecting a center level of said signal and correcting an error thereof is provided. Said circuit can accomplish the detection of the center level correctly always even if there exist cords with various lengths in a length of “1” or “0” of a synchronizing signal at beginning of communication and during communication, and yet frequency variation happens at that time. Said circuit has sample hold circuits SH1 and SH2 each of which are provided so as to correspond to “1” and “0” of an input demodulated data signal. In said circuit a center level value is an average value of voltages held in said sample hold circuits when said signal changes from “1” to “0” or “0” to “1” and a center level value is obtained by adding or subtracting a voltage of ½ of difference between two hold voltages held in another sample hold circuit SH3 to or from a hold voltage in a receiving side at present time when said signal keeps “1” or “0” continuously.

Abstract: An FSK signal generator comprises a pulse generator which generates a first clock pulse of a frequency n, a second clock pulse of a frequency n/2, and a square wave pulse of a frequency n/2, a first bandpass filter which outputs a first carrier signal of a frequency n by driving of the second clock pulse, a second bandpass filter which outputs a second carrier signal of a frequency 1.5n by driving of the second clock pulse, a carrier signal selection circuit constituted of first through fourth controllable switches supplied with the first and second carrier signals and their phase-inverted signals, and a controller which generates select signals formed according to respective polarities of a data signal, an output FSK signal and a square wave pulse upon the supply of the first clock pulse.