Patents by Inventor Kazuo Nakazato

Kazuo Nakazato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200327562
    Abstract: A vending machine includes a storage to store product management data in which an on-sale product management numbers is associated with product management content; an input and output unit to input and output the product management data; and an update control unit configured to update the product management data. Further, the update control unit collectively receives all the product management data including a part to be updated, stores all the product management data as update target product management data, displays the update target product management data including confirmation target information and stores the update target product management data as updated product management data.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: THE COCA-COLA COMPANY
    Inventors: Takashi TANAZAWA, Minoru MURAYAMA, Kazuo TSUNODA, Yusuke NAKAJIMA, Yasuo NAKAZATO, Yasuhiro YAMAZAKI, Takashi NISHIYAMA
  • Publication number: 20180180566
    Abstract: Provided is a reference electrode-holding member that is highly operable and that has conductive lines that are not easily contaminated. Also provided is a substance detection device.
    Type: Application
    Filed: March 4, 2016
    Publication date: June 28, 2018
    Inventor: Kazuo NAKAZATO
  • Patent number: 8129978
    Abstract: To realize a small size and high detection accuracy in a substance detection apparatus. A charge detection field effect transistor and a control circuit therefor are provided in each cell, and the control circuit controls the charge detection field effect transistor so that the drain-source voltage and the drain current of the charge detection field effect transistor are always maintained constant. The control circuit may be formed in a CMOS configuration including a small number of elements in a small area using a standard CMOS integrated circuit technique.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: March 6, 2012
    Assignee: National University Corporation Nagoya University
    Inventor: Kazuo Nakazato
  • Publication number: 20100007326
    Abstract: [Object] To realize a small size and high detection accuracy in a substance detection apparatus. [Solving Means] A charge detection field effect transistor and a control circuit therefor are provided in each cell, and the control circuit controls the charge detection field effect transistor so that the drain-source voltage and the drain current of the charge detection field effect transistor are always maintained constant. The control circuit may be formed in a CMOS configuration including a small number of elements in a small area using a standard CMOS integrated circuit technique.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 14, 2010
    Inventor: Kazuo Nakazato
  • Publication number: 20070202638
    Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
    Type: Application
    Filed: April 24, 2007
    Publication date: August 30, 2007
    Inventors: Tsuyoshi Tabata, Kazuo Nakazato, Hiroshi Kujirai, Masahiro Moniwa, Hideyuki Matsuoka, Teruaki Kisu, Teruo Kisu, Haruko Kisu, Satoru Haga
  • Patent number: 7244977
    Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: July 17, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Tsuyoshi Tabata, Kazuo Nakazato, Hiroshi Kujirai, Masahiro Moniwa, Hideyuki Matsuoka, Teruo Kisu, legal representative, Haruko Kisu, legal representative, Satoru Haga, Teruaki Kisu, deceased
  • Patent number: 7132713
    Abstract: A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
    Type: Grant
    Filed: April 15, 2002
    Date of Patent: November 7, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshikazu Shimada, Hideo Sunami, Tatsuya Teshima, Toshiyuki Mine, Ken Yamaguchi
  • Patent number: 7023721
    Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: April 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Publication number: 20060035434
    Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
    Type: Application
    Filed: October 10, 2002
    Publication date: February 16, 2006
    Inventors: Tsuyoshi Tabata, Kazuo Nakazato, Hiroshi Kujirai, Masahiro Moniwa, Hideyuki Matsuoka, Teruaki Kisu, Teruo Kisu, Haruko Kisu, Satoru Haga
  • Patent number: 6987043
    Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: January 17, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., LTD
    Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruo Kisu, legal representative, Haruko Kisu, legal representative, Hideyuki Matsuoka, Tsuyoshi Tabata, Satoru Haga, Teruaki Kisu, deceased
  • Publication number: 20050162894
    Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.
    Type: Application
    Filed: March 22, 2005
    Publication date: July 28, 2005
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Patent number: 6876569
    Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: April 5, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Publication number: 20050051805
    Abstract: A transistor device comprising source and drain regions (S, D), a nanotube structure (2, 3) providing a path for electrical charge carriers between the source and drain regions, and a gate region (4). The nanotube structure has its conduction band structure locally modified in the gate region, e.g. by doping, for controlling the passage of the charge carriers in the path. The device can be used as a flash memory or as a memory element in a DRAM.
    Type: Application
    Filed: July 12, 2004
    Publication date: March 10, 2005
    Inventors: Byong Kim, Kazuo Nakazato, Hiroshi Mizuta
  • Patent number: 6861692
    Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
    Type: Grant
    Filed: January 8, 2003
    Date of Patent: March 1, 2005
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruo Kisu, Haruko Kisu, Hideyuki Matsuoka, Tsuyoshi Tabata, Teruaki Kisu
  • Patent number: 6825527
    Abstract: A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
    Type: Grant
    Filed: June 5, 2003
    Date of Patent: November 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Sunami, Kiyoo Itoh, Toshikazu Shimada, Kazuo Nakazato, Hiroshi Mizuta
  • Patent number: 6787411
    Abstract: Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: September 7, 2004
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Teruaki Kisu, Kazuo Nakazato, Masahito Takahashi
  • Publication number: 20040170050
    Abstract: A semiconductor integrated circuit device including a plurality of memory cells, each having a storage MOSFET holding information in a gate of the storage MOSFET, a write transistor supplying a write information voltage corresponding to the information to the gate storage MOSFET, and a capacitor having first and second terminals. Word lines and data lines are coupled with the memory cells. The first capacitor terminal is coupled with one of the word lines and the second capacitor terminal is coupled with the gate of the storage MOSFET. In a read operation of the semiconductor integrated circuit device, the gate voltage of the storage MOSFET is boosted by a transition of the word line from a first voltage to a second voltage greater than the first voltage.
    Type: Application
    Filed: March 10, 2004
    Publication date: September 2, 2004
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Patent number: 6762951
    Abstract: A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first an
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: July 13, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoo Itoh, Kazuo Nakazato
  • Patent number: 6753568
    Abstract: A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
    Type: Grant
    Filed: July 28, 1999
    Date of Patent: June 22, 2004
    Assignee: Hitachi, LTD.
    Inventors: Kazuo Nakazato, Kiyoo Itoh, Hiroshi Mizuta, Toshihiko Sato, Toshikazu Shimada, Haroon Ahmed
  • Publication number: 20040000690
    Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
    Type: Application
    Filed: January 8, 2003
    Publication date: January 1, 2004
    Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruaki Kisu, Teruo Kisu, Hideyuki Matsuoka, Tsuyoshi Tabata