Patents by Inventor Kazuo Shimokawa

Kazuo Shimokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438935
    Abstract: According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuo Shimokawa, Masayuki Uchida, Akira Tojo, Masatoshi Tanabe, Takashi Ito
  • Publication number: 20190287952
    Abstract: According to one embodiment, the first end part of the first semiconductor chip in a lower stage protrudes to a larger extent in a first direction than the first end part of the first semiconductor chip in an upper stage. The second end part of the second semiconductor chip in a lower stage protrudes to a larger extent in a second direction opposite from the first direction than the second end part of the second semiconductor chip in an upper stage. The first interlayer semiconductor chip includes a first portion, a second portion, and a third electrode pad. The first portion overlaps the first chip group. The second portion protrudes in the second direction beyond the first chip group and the second chip group and is thicker than the first portion. The third electrode pad is provided on the second portion and bonded with the third metal wire.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuo SHIMOKAWA, Masayuki UCHIDA, Akira TOJO, Masatoshi TANABE, Takashi ITO
  • Publication number: 20190287895
    Abstract: A semiconductor device includes a redistribution layer, a bump bonded to a first surface of the redistribution layer, and a chip bonded to a second surface of the redistribution layer. The redistribution layer includes an insulating layer, a conductive member connecting the bump to the chip and being provided inside the insulating layer, a bonding electrode connected between the conductive member and the bump, and a conductive layer provided between the insulating layer and the conductive member and between the bonding electrode and the conductive member. A resistivity of the conductive member is lower than a resistivity of the conductive layer.
    Type: Application
    Filed: January 25, 2019
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki TAJIMA, Kazuo SHIMOKAWA
  • Publication number: 20190287945
    Abstract: A semiconductor device includes a base, a first semiconductor chip mounted on the base, and a second semiconductor chip provided above the first semiconductor chip. The second semiconductor chip includes a first portion, a second portion including a region directly above a center of the first semiconductor chip, and a third portion including part of a portion of the second semiconductor chip other than a region directly above the first semiconductor chip. The second portion is thicker than the first portion. The third portion is thicker than the second portion and is disposed at a position sandwiching the first semiconductor chip.
    Type: Application
    Filed: February 11, 2019
    Publication date: September 19, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA MEMORY CORPORATION
    Inventors: Akira TOJO, Kazuo Shimokawa, Masayuki Uchida, Takashi Ito, Masatoshi Tanabe
  • Publication number: 20190267350
    Abstract: According to one embodiment, a semiconductor device includes a re-interconnection layer, bumps, chips, and a resin member. The bumps are provided on a first surface of the re-interconnection layer. The chips are stacked on a second surface of the re-interconnection layer. The resin member is provided on the second surface, and covers the chips. The re-interconnection layer includes an insulating layer, an interconnection, a first via, an electrode layer, and a second via. The interconnection is provided in the insulating layer. The first via is provided in the insulating layer and connected to the interconnection. The electrode layer is provided in the insulating layer, formed of a metal material different from a material of the first via, exposed on the first surface, and connected to the first via and the bumps. The second via is provided in the insulating layer, and connected to the interconnection and the chips.
    Type: Application
    Filed: August 8, 2018
    Publication date: August 29, 2019
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Takayuki TAJIMA, Yoichiro KURITA, Kazuo SHIMOKAWA
  • Publication number: 20190252199
    Abstract: An etching method according to an embodiment includes forming an uneven structure including a projection on a surface of a semiconductor substrate; forming a catalyst layer including a noble metal on the surface selectively at a top surface of the projection; and supplying an etchant to the catalyst layer to cause an etching of the semiconductor substrate with an assist from the noble metal as a catalyst.
    Type: Application
    Filed: February 5, 2019
    Publication date: August 15, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro MATSUO, Susumu OBATA, Mitsuo SANO, Kazuhito HIGUCHI, Kazuo SHIMOKAWA
  • Publication number: 20190067250
    Abstract: A semiconductor device includes a base including interconnects, a first semiconductor chip including a first semiconductor element portion, and a second semiconductor chip including a second semiconductor element portion. The second semiconductor chip is electrically connected to the first semiconductor chip via at least one of the interconnects. The second semiconductor chip includes a first region, a first portion, and a second portion. The first region includes the second semiconductor element portion. The first portion is continuous with the first region. The second portion is continuous with the first region and is separated from the first portion in a second direction crossing a first direction. The first direction is from the base toward the first region. The second portion, the first portion, and at least a portion of the first semiconductor chip each is positioned between the base and the first region.
    Type: Application
    Filed: June 4, 2018
    Publication date: February 28, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tatsuya Kobayashi, Masayuki Uchida, Takashi Ito, Kazuo Shimokawa
  • Patent number: 10128153
    Abstract: a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: November 13, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takayuki Tajima, Kazuo Shimokawa, Tatsuya Kobayashi
  • Publication number: 20180286819
    Abstract: A semiconductor device includes a substrate, a device layer, and a film. The substrate includes a first semiconductor element, and has a first surface, a second surface, and a side surface between the first surface and the second surface. The device layer includes a second semiconductor element electrically connected to the first semiconductor element, and is provided on the first surface of the substrate. The film includes a first film including a first region, a second region, and a third region. The substrate is positioned between the first region and the device layer in a first direction. The substrate is positioned between the second region and the third region in a second direction crossing the first direction. The first film fills the unevenness of the second surface and the side surface.
    Type: Application
    Filed: March 6, 2018
    Publication date: October 4, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akira Tojo, Tatsuya Kobayashi, Kazuo Shimokawa
  • Patent number: 10090158
    Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 2, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro Matsuo, Yusaku Asano, Kazuhito Higuchi, Kazuo Shimokawa
  • Patent number: 9885762
    Abstract: A magnetic shielded package includes a magnetic device, a first magnetic shield member, and a second magnetic shield member. The first magnetic shield member is disposed below the magnetic device. The second magnetic shield member is disposed on the first magnetic shield member so as to cover the magnetic device. An opening portion is formed in the first magnetic shield member (i) at such a position as not to be adjacent to an outer circumference of the first magnetic shield member or (ii) an upper wall of the second magnetic shield member.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: February 6, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiju Yamada, Mikiya Iida, Kei Masunishi, Kazuo Shimokawa, Hideaki Fukuzawa, Michiko Hara
  • Publication number: 20180033634
    Abstract: An etching method according to an embodiment includes forming a catalyst layer made of a first noble metal or the combination of the second noble metal and the metal other than noble metals on a surface made of a semiconductor, the catalyst layer including a first portion and a second portion, the first portion covering at least a part of the surface, the second portion being located on the first portion, having an apparent density lower than that of the first portion, and being thicker than the first portion; and supplying an etchant to the catalyst layer to cause an etching of the surface with an assist from the catalyst layer as a catalyst.
    Type: Application
    Filed: July 25, 2017
    Publication date: February 1, 2018
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiichiro MATSUO, Yusaku Asano, Kazuhito Higuchi, Kazuo Shimokawa
  • Publication number: 20170050842
    Abstract: According to one embodiment, a printed wiring board includes a first magnetic layer, a second magnetic layer, an insulating layer, a first conductor layer, and a second conductor layer. The insulating layer is provided between the first magnetic layer and the second magnetic layer. The first conductor layer is provided between the insulating layer and the first magnetic layer. The second conductor layer is provided between the insulating layer and the second magnetic layer.
    Type: Application
    Filed: August 19, 2016
    Publication date: February 23, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiju YAMADA, Kazuo SHIMOKAWA, Tomohiro IGUCHI, Michiko HARA, Motomichi SHIBANO
  • Publication number: 20160365340
    Abstract: a method of fabricating a semiconductor device is described below. The method includes stacking a plurality of semiconductor chips on each of regions in a substrate having a plurality of first grooves extending in a first direction and a plurality of second grooves extending in a second direction intersecting the first direction, the region being defined by the first grooves and the second grooves, providing an encapsulation portion covering a side of the substrate on which the semiconductor chips are stacked, removing a surface portion of the substrate on the opposite side to the side on which the semiconductor chips are stacked to expose the first grooves and the second grooves, and cutting the encapsulation portion along the first grooves and of second grooves. The device and the method can provide higher productivity.
    Type: Application
    Filed: June 14, 2016
    Publication date: December 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takayuki TAJIMA, Kazuo Shimokawa, Tatsuya Kobayashi
  • Patent number: 9431588
    Abstract: Provided is an optical semiconductor device includes: a light-emitting layer having a first main surface, a second main surface opposed to the first main surface, a first electrode and a second electrode which are formed on the second main surface; a fluorescent layer provided on the first main surface; a light-transmissive layer provided on the fluorescent layer and made of a light-transmissive inorganic material; a first metal post provided on the first electrode; a second metal post provided on the second electrode; a sealing layer provided on the second main surface so as to seal in the first and second metal posts with one ends of the respective first and second metal posts exposed; a first metal layer provided on the exposed end of the first metal post; and a second metal layer provided on the exposed end of the second metal post.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 30, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuo Shimokawa, Takashi Koyanagawa, Takeshi Miyagi, Akihiko Happoya, Kazuhito Higuchi, Tomoyuki Kitani
  • Publication number: 20160091575
    Abstract: A magnetic shielded package includes a magnetic device, a first magnetic shield member, and a second magnetic shield member. The first magnetic shield member is disposed below the magnetic device. The second magnetic shield member is disposed on the first magnetic shield member so as to cover the magnetic device. An opening portion is formed in the first magnetic shield member (i) at such a position as not to be adjacent to an outer circumference of the first magnetic shield member or (ii) an upper wall of the second magnetic shield member.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventors: Keiju YAMADA, Mikiya llDA, Kei MASUNISHI, Kazuo SHIMOKAWA, Hideaki FUKUZAWA, Michiko HARA
  • Patent number: 9236551
    Abstract: According to one embodiment, there is provided a light-emitting device including a light-emitting section, a thermal radiation member, and a heat conduction layer. The light-emitting section includes a mounting substrate section and a light-emitting element section. The mounting substrate section includes a substrate, a first metal layer, and a second metal layer. The substrate includes a first principal plane including a mounting region and a second principal plane. The first metal layer includes mounting patterns provided in the mounting region. The light-emitting element section includes semiconductor light-emitting elements and a wavelength conversion layer. The semiconductor light-emitting elements are connected to the mounting patterns. The luminous existence of the light-emitting element section is equal to or higher than 10 lm/mm2 and equal to or lower than 100 lm/mm2. The thermal radiation member has an area equal to or larger than five times the area of the mounting region.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: January 12, 2016
    Assignee: Toshiba Lighting & Technology Corporation
    Inventors: Kiyoshi Nishimura, Kazuo Shimokawa, Nobuhiko Betsuda, Akihiro Sasaki, Miho Watanabe, Hirotaka Tanaka, Takuya Honma, Katsuhisa Matsumoto, Hideki Okawa
  • Patent number: 9202982
    Abstract: A semiconductor light emitting device includes a light emitting unit, a first and second electrode, a first and second metal pillar, a sealing unit, a rectifying element, and a first and second interconnection. The light emitting unit includes a first and second semiconductor layer, and a light-emitting layer. The light-emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light-emitting layer. The first electrode is provided on the first semiconductor layer. The second electrode is provided on the second semiconductor layer. The first metal pillar is electrically connected to the first electrode. The second metal pillar is electrically connected to the second electrode. The sealing unit seals the first metal pillar and the second metal pillar. The rectifying element is provided below the first semiconductor layer, including a rectifying unit.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: December 1, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Susumu Obata, Toshiya Nakayama, Hisashi Ito, Akiya Kimura, Kazuo Shimokawa, Kazuhito Higuchi, Akihiro Kojima, Miyoko Shimada, Yoshiaki Sugizaki, Hideto Furuyama
  • Patent number: 9087974
    Abstract: A semiconductor light emitting device includes a light emitting unit, a first and second conductive pillar, a sealing unit, and a first and second terminal. The light emitting unit includes a first and second semiconductor layer and a light emitting layer. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer is provided on the light emitting layer. The first conductive pillar is provided on the first semiconductor layer. The second conductive pillar is provided on the second semiconductor layer. The sealing unit covers side faces of each of the light emitting unit, the first conductive pillar, and the second conductive pillar. The first terminal is provided on the first conductive pillar and on the sealing unit. The second terminal is provided on the second conductive pillar and on the sealing unit.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: July 21, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akiya Kimura, Kazuhito Higuchi, Kazuo Shimokawa, Susumu Obata, Toshiya Nakayama, Hisashi Ito
  • Publication number: 20150144970
    Abstract: According to an exemplary embodiment, there is provided a light emitting device including a ceramic substrate, first to fourth connectors, a plurality of semiconductor light emitting elements, and a first metal layer. The ceramic substrate is provided with a first main surface including first to fourth sides and first to fourth corner portions, and the first main surface includes a mounting region, and first to fourth connector region provided respectively between the first to fourth corner portion and the mounting region. The plurality of semiconductor light emitting elements is provided on the mounting region. The first to fourth connectors are respectively provided on the first to fourth connector regions. A first metal layer is provided between the plurality of semiconductor light emitting elements and the ceramic substrate, and including first to fourth connector electrode portions electrically connected respectively to the first to fourth connectors.
    Type: Application
    Filed: July 18, 2014
    Publication date: May 28, 2015
    Applicant: TOSHIBA LIGHTING & TECHNOLOGY CORPORATION
    Inventors: Nobuhiko Betsuda, Akihiro Sasaki, Hideki Okawa, Kazuo Shimokawa