Abstract: A network relaying apparatus and method for detecting a flow at high speed and performing a variety of control operations including quality-of-service (QoS) control and filtering at high speed. A transfer engine stores the packet received through a network interface, in a packet buffer, and stores the header information in a header RAM. A search engine searches the transfer control information including the transfer destination information and the action information according to the header information, and writes it in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch operates to switch the output packet to the routing processor of the final destination.

Abstract: A network relaying apparatus and method for routing and transferring packets at high speed. A transfer engine stores the packets received through a network interface in a packet buffer, and stores the header information in a header RAM. A search engine searches the transfer control information including the transfer destination information and the action information in accordance with the header information, and writes it in the header RAM. The transfer engine produces an output packet based on the information stored in the packet buffer and the header RAM and outputs it to the transfer destination. A switch switches the output packet to the routing process of the destination. The transfer engine executes the receiving process and the transmission process, and the search engine executes the input search process and the output search process. Each of these processes is executed by pipelining control using a required table independently.

Abstract: A system includes at least two servers for executing the same application protocol among a plurality of servers, load balancing apparatus respectively connected to the servers, and a router connected to these load balancing apparatuses and to a network. Receiving an access packet from the network, the router selects and routes an arbitrary load balancing apparatus. Receiving the access packet, each load balancing apparatus selects an arbitrary server and transmits the access packet.

Abstract: Each of a plurality of data processing units that form a network relaying apparatus has a memory controller, a network controller, a processor, and independently accessible first and second memories. The memory controller includes a header information register for storing header information such as a header start position in a packet and a header length; a header position detection circuit for detecting a header position in the packet based on the header information contained in the header information register; and an inter-data processing unit transfer circuit for sending and receiving a packet to and from another data processing unit. The data processing unit stores into the first memory a packet received from the network or a packet transferred from another data processing unit, and at the same time stores only a header portion of the packet into the second memory.

Abstract: With respect to a router in a backup path in an MPLS network adopting a label stack method, it is an object of the present invention to achieve the same quality-guarantee control as the one performed in a current path. In a packet transfer device accommodating first and second output lines, when the first line has a fault, upon a first packet being received, communication quality information in a header of the first packet is copied. Further, a first header containing the copied priority information and a new label is added to the first packet, and a packet to which the first packet is added is outputted to a second output line. When a second packet is received, communication quality information in a header of the second packet is copied, a second header containing the copied priority information and the new label is added to the second packet, and a packet to which the second packet is added is outputted to the second output line.

Abstract: A network routing apparatus in which packet forwarding units for performing a packet forwarding process are arranged in parallel to one another, a packet distribution unit for distributing packets to the packet forwarding units arranged in parallel to one another, a packet rearrangement unit for rearranging outputs of the packet forwarding units are provided in the network routing apparatus, and packet retrieving units for retrieving packet headers in the packet forwarding units are further arranged in parallel to one another.

Abstract: The present invention provides a VPN edge router with the ability of identifying VPNs by using the identifiers of logical channels multiplexed on a single input line.

Abstract: An information processing unit having a bus controller connected to a plurality of different shared buses which can independently control the different shared buses, and a double adaptor connected to the different shared buses which can independently control the different shared buses, wherein first and second ones of the shared buses are independently controlled to send data from the bus controller to the double adaptor, and from the double adaptor to the bus controller, respectively.

Abstract: A display control system provided between a computer and a display device includes a plurality of display control LSI's for data transfer and also displays image data stored in a plurality of image memories having planes on the display device by controlling plane groups which include one or more planes. Each display control LSI includes an enable generator for generating a synchronization enabling signal in accordance with LSI designation information and an input/output buffer for outputting a synchronization signal in response to the enabling signal. A synchronization signal from one of the plurality of display control LSI's designated by the LSI designation information is supplied to the plurality of display control LSI's inclusive of the designated display control LSI through a signal line to allow the plurality of display control LSI's to operate with each other, thereby making it possible to produce and display data to be simultaneously on the display device.

Abstract: An image data processing system which includes an image memory and an image processor for performing coordinate transformation of source image data expressed by two dimensional coordinates.

Abstract: An ultrasonic flaw detecting apparatus of electronically scanning type comprises a plurality of ultrasonic vibrator elements disposed in an arcuate array, wherein groups of N vibrator elements arrayed in the circumferential direction of an object under test are sequentially changed over to one another on one-by-one base to thereby scan an object under test with ultrasonic beams. By controlling phases of pulse signals applied to the individual vibrator elements, a region of focus of the ultrasonic beams is set at a predetermined depth of the object under test. For reception, only the echoes reflected from a predetermined focal range are selectively extracted by providing corresponding window or gate means.