Patents by Inventor Kazuo Sukegawa
Kazuo Sukegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8507377Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: GrantFiled: April 21, 2010Date of Patent: August 13, 2013Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20100240211Abstract: A method of manufacturing a semiconductor device including an integrated circuit part in which an integrated circuit is formed and a main wall part including metal films surrounding said integrated circuit part, includes the step of selectively forming a sub-wall part including metal films between the integrated circuit part and the main wall part, in parallel to formation of the integrated circuit part and the main wall part. A sub-wall part which is in an “L” shape is provided between each corner of the main wall part and the integrated circuit part of the resulting semiconductor device.Type: ApplicationFiled: April 21, 2010Publication date: September 23, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA
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Patent number: 7755169Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: January 22, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20090127666Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: January 22, 2009Publication date: May 21, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Kenichi WATANABE, Michiari KAWANO, Hiroshi NAMBA, Kazuo SUKEGAWA, Takumi HASEGAWA, Toyoji SAWADA, Junichi Mitani
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Patent number: 7498659Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: February 13, 2006Date of Patent: March 3, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 7129565Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: GrantFiled: January 24, 2003Date of Patent: October 31, 2006Assignee: Fujitsu LimitedInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Publication number: 20060194124Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: February 13, 2006Publication date: August 31, 2006Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada
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Patent number: 7005755Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: GrantFiled: December 29, 2003Date of Patent: February 28, 2006Assignee: Fujitsu LimitedInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Patent number: 6858914Abstract: A semiconductor device has: a semiconductor substrate having a principal surface; a fuse circuit formed above the principal surface, the fuse circuit having fuse elements each having a predetermined breaking point; a first trench isolation region formed in a surface layer of the semiconductor substrate under the fuse circuit; and a plurality of active region dummies formed through the first trench isolation region in an area excepting a predetermined area around the predetermined breaking point. Although a dummy structure is formed also in a fuse circuit, a breaking margin is prevented from being lowered and a substrate damage is avoided, while surface flatness and line width controllability are ensured.Type: GrantFiled: October 30, 2003Date of Patent: February 22, 2005Assignee: Fujitsu LimitedInventors: Ryota Nanjo, Satoshi Otsuka, Toyoji Sawada, Kazuo Sukegawa
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Publication number: 20040135226Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: ApplicationFiled: December 29, 2003Publication date: July 15, 2004Applicant: FUJITSU LIMITEDInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Publication number: 20040089915Abstract: A semiconductor device has: a semiconductor substrate having a principal surface; a fuse circuit formed above the principal surface, the fuse circuit having fuse elements each having a predetermined breaking point; a first trench isolation region formed in a surface layer of the semiconductor substrate under the fuse circuit; and a plurality of active region dummies formed through the first trench isolation region in an area excepting a predetermined area around the predetermined breaking point. Although a dummy structure is formed also in a fuse circuit, a breaking margin is prevented from being lowered and a substrate damage is avoided, while surface flatness and line width controllability are ensured.Type: ApplicationFiled: October 30, 2003Publication date: May 13, 2004Applicant: FUJITSU LIMITEDInventors: Ryota Nanjo, Satoshi Otsuka, Toyoji Sawada, Kazuo Sukegawa
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Patent number: 6706610Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: GrantFiled: August 30, 2002Date of Patent: March 16, 2004Assignee: Fujitsu LimitedInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Patent number: 6686644Abstract: A high-strength protective member made of tungsten is disposed under a disconnecting point of a fuse. This protective member is formed simultaneously with formation of a via contact portion which connects the fuse with wiring, for example.Type: GrantFiled: March 22, 2002Date of Patent: February 3, 2004Assignee: Fujitsu LimitedInventors: Tsutomu Tatematsu, Kengi Togashi, Masayuki Nakada, Toyoji Sawada, Kazuo Sukegawa, Tomoyuki Yamada, Yoshikazu Arisaka
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Publication number: 20030173675Abstract: A main wall part is provided so as to surround an integrated circuit part. A sub-wall part which is in “L” shape is provided between each corner of the main wall part and the integrated circuit part. Therefore, even if the stress is concentrated due to heat treatment or the like, the stress is dispersed to the main wall part and the sub-wall part, and hence peeling between layers and a crack are unlikely to occur, as compared with the conventional art. Further, even if the crack and the like occur at the corner, moisture from the outside hardly reaches the integrated circuit part when the main wall part and the sub-wall part are coupled to each other. For this reason, it is possible to ensure an extremely high moisture resistance.Type: ApplicationFiled: January 24, 2003Publication date: September 18, 2003Applicant: FUJITSU LIMITEDInventors: Kenichi Watanabe, Michiari Kawano, Hiroshi Namba, Kazuo Sukegawa, Takumi Hasegawa, Toyoji Sawada, Junichi Mitani
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Publication number: 20030008472Abstract: A semiconductor device formed on a SOI substrate includes isolation trenches formed in a first region and reaching an insulation layer buried in the SOI substrate, and alignment marks formed in a second region and consisting of grooves extending into a support substrate.Type: ApplicationFiled: August 30, 2002Publication date: January 9, 2003Applicant: FUJITSU LIMITEDInventors: Tetsuo Yoshimura, Shinji Kuzuya, Kazuo Sukegawa, Tetsuo Izawa
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Publication number: 20020153588Abstract: A high-strength protective member made of tungsten is disposed under a disconnecting point of a fuse. This protective member is formed simultaneously with formation of a via contact portion which connects the fuse with wiring, for example.Type: ApplicationFiled: March 22, 2002Publication date: October 24, 2002Applicant: Fujitsu Limited of KawasakiInventors: Tsutomu Tatematsu, Kengi Togashi, Masayuki Nakada, Toyoji Sawada, Kazuo Sukegawa, Tomoyuki Yamada, Yoshikazu Arisaka