Patents by Inventor Kazuo Takaragi

Kazuo Takaragi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6873706
    Abstract: To provide a secure cryptographic device such as an IC card which can endure TA (Timing Attack), DPA (Differential Power Analysis), SPA (Simple Power Analysis), or the like as an attaching method of presuming secret information held therein, when the secret information held in the card or another information which is used in the secret information or an arithmetic operation using such secret information when such an arithmetic operation is performed is shown by a plurality of expressing methods and the arithmetic operation is performed, thereby making an arithmetic operation processing method different each time the arithmetic operation is performed and making each of an arithmetic operation time, an intensity of a generated electromagnetic wave, and a current consumption different.
    Type: Grant
    Filed: September 29, 1999
    Date of Patent: March 29, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiko Miyazaki, Kazuo Takaragi, Yasuko Fukuzawa
  • Patent number: 6816969
    Abstract: In a signature generating method where not necessarily all of a plurality of signature generating devices work together each time to generate signatures, the present invention seeks to correctly and securely reflect data relating to previous signatures. When generating signatures, the data used for the next signature is sent beforehand to the other signature generating devices. Also, when generating signatures, at least one of the devices is used consecutively, thus allowing history data to be shared during signature generation.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kunihiko Miyazaki, Ryoichi Sasaki, Kazuo Takaragi, Seiichi Susaki, Hisanori Mishima, Takeshi Matsuki, Kunihito Takeuchi, Mitsuru Iwamura, Tsutomu Matsumoto
  • Publication number: 20040156176
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Application
    Filed: October 20, 2003
    Publication date: August 12, 2004
    Applicant: HITACHI, LTD.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6731509
    Abstract: In a method of mounting a planar electronic circuit chip onto a flexible sheet together with another planar electronic element, the electronic circuit part and the another electric element are selected so that the planar surface of the another electric element is greater than the planar surface of the electronic circuit chip, and the another electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the another electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.
    Type: Grant
    Filed: September 14, 2001
    Date of Patent: May 4, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Sobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20040060978
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from or in which information can be read out or written and having visible information.
    Type: Application
    Filed: September 30, 2003
    Publication date: April 1, 2004
    Applicants: HITACHI, LTD., HITACHI RESEARCH INSTITUTE
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Patent number: 6714648
    Abstract: In an IC card incorporating residual multiplier hardware for implementing a high-speed algorithm for a residual multiplication arithmetic, a method and a device capable of executing a public key encryption processing such as an elliptic curve encryption processing at a high speed. Residual arithmetic succeeding to generation of a random number and residual arithmetic in a signature generating processing can be executed by using a residual multiplier. Further, in order to use effectively the residual multiplier for arithmetic operation on an elliptic curve, the point on the elliptic curve is transformed from a two-dimensional affine coordinate system to a three-dimensional coordinate system. Additionally, multiplicative inverse arithmetic for realizing reverse transformation from the three-dimensional coordinate system to the two-dimensional affine coordinate system as well as for determining a signature s can be executed only with the residual multiplication arithmetic.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miyazaki, Kazuo Takaragi
  • Patent number: 6683956
    Abstract: An encrypting conversion apparatus, a decrypting conversion apparatus, a cryptographic communication system and an electronic toll collection apparatus are provided which are capable of changing algorithms of cryptographic conversion to hide the algorithm in use from a third party so that the apparatuses and system are resistant against a cryptographic attack from the third party and can operate at high speed. In the cryptographic communication system.
    Type: Grant
    Filed: June 1, 1999
    Date of Patent: January 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Aikawa, Shigeru Hirahata, Kazuo Takaragi, Yoshimichi Kudo
  • Patent number: 6659353
    Abstract: A method of checking sheets as to forgery thereof, the sheet being provided with an electronic circuit chip from which information can be read out or written and having visible information. The method includes a step of encrypting the visible information of the sheet and storing the encrypted visible information in the electronic circuit chip, and a step of determining discriminatively the authenticity of the sheet by comparing the visible information of the sheet with the information stored in the electronic circuit chip.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: December 9, 2003
    Assignees: Hitachi, Ltd., Hitachi Research Institute
    Inventors: Chikashi Okamoto, Kazuo Takaragi, Kazutaka Tsuji, Mitsuo Usami, Chizuko Yasunobu, Asahiko Isobe, Yasuhiro Tsunemi, Hiroyuki Yagi
  • Publication number: 20030212828
    Abstract: A time stamp generating system has a time distribution server for generating time data depending on time and a user PC for holding time certification objective digital data. The time distribution server generates time data corresponding to a time point and distributes the time data. The user PC calculates time stamp generating data by using the time certification objective data as an input, acquires the time data generated by the time distribution server, and processes the time data on the basis of the time stamp generating data to obtain a time stamp.
    Type: Application
    Filed: August 20, 2002
    Publication date: November 13, 2003
    Inventors: Kunihiko Miyazaki, Seiichi Susaki, Kazuo Takaragi, Hiroshi Yoshiura, Takeshi Matsuki, Hisashi Toyoshima, Mitsuru Iwamura, Tsutomu Matsumoto, Ryoichi Sasaki
  • Publication number: 20030169149
    Abstract: The present invention provides a RFID tag structure suited to determining the authenticity of an article or part, and also provides an information processing system for reading RFID tags, which enables authenticity determinations of articles or parts to be carried out with accuracy using Read only RFID tags.
    Type: Application
    Filed: March 5, 2003
    Publication date: September 11, 2003
    Inventors: Masaru Ohki, Hideki Tokuyama, Rei Itsuki, Shojiro Asai, Kazuo Takaragi, Atsushi Tanaka
  • Patent number: 6606385
    Abstract: Encrypting/decrypting conversion method and apparatus capable of controlling dynamically cyclic shift independent of data to undergo encrypting/decrypting conversion includes two or more different fixed circulating shift processing means for shifting cyclically the data by a fixed bit number leftward or rightward, a cyclic shift processing selecting means for selecting fixed cyclic shift processing means. The selecting sequence determined by the cyclic shift processing means is determined on the basis of data for determining the shift number selecting sequence.
    Type: Grant
    Filed: August 4, 1998
    Date of Patent: August 12, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Aikawa, Kazuo Takaragi, Hiroyuki Koreeda, Manabu Sasamoto, Hiroo Okamoto, Takaharu Noguchi, Soichi Furuya, Shigeru Hirahata
  • Patent number: 6592032
    Abstract: A method is adopted in a control apparatus for controlling ID information stored in a storage medium in conjunction with a terminal for reading the ID information from the storage medium and used to catalog information for the storage medium into a memory employed in the control apparatus. In an operation to catalog information into the memory of the control apparatus, the terminal receives the information, reads the ID information from the storage medium and transmits the information and the ID information to the control apparatus and the control apparatus catalogs the information and the ID information in the memory by associating the information with the ID information.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: July 15, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takaragi, Chikashi Okamoto
  • Publication number: 20030105853
    Abstract: In a handling support method for supporting handling of an object, a distributed system including at least one attribute information management server for managing attribute information of an object in correspondence with identification information given to the object, at least one identification information management server for managing the attribute information management server in correspondence with the identification information, and at least one supporting server for supporting handling of the object in accordance with the attribute information is connected to a user terminal over a network. Then, based on identification information obtained by the user terminal, the identification information management server specifies an address of the attribute information management server for managing attribute information of the object to which the identification information is given.
    Type: Application
    Filed: November 27, 2002
    Publication date: June 5, 2003
    Inventors: Hajime Morito, Yasuko Fukuzawa, Kazuo Takaragi, Shyojiro Asai
  • Publication number: 20030026430
    Abstract: An encrypting conversion apparatus, a decrypting conversion apparatus, a cryptographic communication system and an electronic toll collection apparatus are provided which are capable of changing algorithms of cryptographic conversion to hide the algorithm in use from a third party so that the apparatuses and system are resistant against a cryptographic attack from the third party and can operate at high speed. In the cryptographic communication system.
    Type: Application
    Filed: September 26, 2002
    Publication date: February 6, 2003
    Inventors: Makoto Aikawa, Shigeru Hirahata, Kazuo Takaragi, Yoshimichi Kudo
  • Publication number: 20030021410
    Abstract: In an IC card incorporating residual multiplier hardware for implementing a high-speed algorithm for a residual multiplication arithmetic, a method and a device capable of executing a public key encryption processing such as an elliptic curve encryption processing at a high speed. Residual arithmetic succeeding to generation of a random number and residual arithmetic in a signature generating processing can be executed by using a residual multiplier. Further, in order to use effectively the residual multiplier for arithmetic operation on an elliptic curve, the point on the elliptic curve is transformed from a two-dimensional affine coordinate system to a three-dimensional coordinate system. Additionally, multiplicative inverse arithmetic for realizing reverse transformation from the three-dimensional coordinate system to the two-dimensional affine coordinate system as well as for determining a signature s can be executed only with the residual multiplication arithmetic.
    Type: Application
    Filed: September 24, 2002
    Publication date: January 30, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Seiji Miyazaki, Kazuo Takaragi
  • Patent number: 6504931
    Abstract: In the process of compressing and encrypting data, without an increase of processing time, a cipher capability is secured against the latest cryptanalysis such as differential and linear cryptanalyses. The differential and linear cryptanalyses are executed to collect plural pairs of plaintext and cryptosystem for the same key and perform the statistical operation for estimating the key. An input/output (I/O) process is executed to receive plaintext data and generate a different key for each data on the random number and set the key to a work key. The encrypted intermediate result or the pre-encrypted result is fed back to permit frequent changing of the work key. The changing operation is executed to change correspondence between the plaintext data and the compressed data in the compressing process.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: January 7, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yoshiura, Kazuo Takaragi, Mayuko Shimizu
  • Patent number: 6499105
    Abstract: This invention provides a method for identifying a purchaser who purchased content from which an illegal copy was produced. A provider system encrypts purchased by the purchaser using a public key of a purchaser system and sends the encrypted content to the purchaser system. The purchaser system creates a digital signature of the content with the use of a private key of its own and embeds the created digital signature into the received content. When an illegal copy is found, the provider system verifies the digital signature, embedded in the illegal copy as a digital watermark, to identify the purchaser who purchased the content from which the illegal copy was produced.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: December 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Yoshiura, Kazuo Takaragi, Ryoichi Sasaki, Seiichi Susaki, Hisashi Toyoshima, Tsukasa Saito
  • Publication number: 20020174369
    Abstract: Techniques of improving the safety of an information processing system at low cost are provided, the information processing system having an OS provided with an access control function based upon discretionary access control for preventing illegal accesses to files. A method and apparatus for providing the information processing system with functions and areas usable only by a specific user different from a system administrator. The areas are provided with an access control function in order to prevent the access control function from being tampered.
    Type: Application
    Filed: February 20, 2002
    Publication date: November 21, 2002
    Applicant: Hitachi, Ltd.
    Inventors: Kunihiko Miyazaki, Shinji Itoh, Hiroshi Yoshiura, Kazuo Takaragi, Masato Arai, Toshiaki Arai, Takeshi Maksuki, Hisashi Toyoshima
  • Patent number: 6477254
    Abstract: In a data encryption/decryption method including an encryption step and a decryption step. In the encryption step, there are prepared n pairs of secret keys and public keys in a public-key cryptographic scheme, where n is a positive integer. A new key is generated in accordance with at least one of the public keys. Data is encrypted in a common-key cryptographic scheme by use of the new key. There is prepared a (k,n) threshold logic (k is an integer equal to or less than n) having terms associated with the new key and the n public keys. A calculation of the threshold logic is conducted by use of the new key and the n public keys, and encrypted data and a result of the calculation of the threshold logic are stored.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miyazaki, Kazuo Takaragi
  • Patent number: 6466668
    Abstract: In an IC card incorporating residual multiplier hardware for implementing a high-speed algorithm for a residual multiplication arithmetic, a method and a device capable of executing public key encryption processing such as an elliptic curve encryption processing at a high speed. Residual arithmetic succeeding to generation of a random number and residual arithmetic in a signature generating processing can be executed by using a residual multiplier. Further, in order to use effectively the residual multiplier for arithmetic operation on an elliptic curve, the point on the elliptic curve is transformed from a two-dimensional affine coordinate system to a three-dimensional coordinate system. Additionally, multiplicative inverse arithmetic for realizing reverse transformation from the three-dimensional coordinate system to the two-dimensional affine coordinate system as well as for determining a signature s can be executed only with the residual multiplication arithmetic.
    Type: Grant
    Filed: January 26, 1999
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Seiji Miyazaki, Kazuo Takaragi