Abstract: The present invention provides a contrast agent which ensures 1) high contrast performance, 2) low toxicity, and 3) a simple production process. The present invention provides a contrast agent containing a silsesquioxane represented by General Formula (I), wherein R1, the same or different, is a substituent bonded to Si through a carbon atom, the substituent having, at its terminal, a group represented by General Formula (II), wherein p represents an integer of from 1 to 5; q is the same or different, and represents an integer of from 1 to 5; R2 is the same or different, and represents hydrogen atom, alkyl group, aralkyl group or acyl group, or a group represented by General Formula (III), wherein p, q and R2 are the same as above.

Abstract: The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus 10 for manufacturing metal plate chip resistors including cutting mold 21 for cutting intermediate product strip 14 transversely to obtain worked product chip 16a, ohm meter 22 for measuring the resistance of the worked product chip 16a, control device 23 having a calculating part for performing a calculation using the resistance measured by the ohm meter 22 to work out a width in which the strip 14 is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjusting means 26, 27 for making an adjustment so that the strip 14 is to be cut transversely in the width obtained from the calculating part.

Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.

Abstract: A process in which a phenol derivative is iodinated to produce a 2-iodophenol or 2,6-diiodophenol derivative substituted with iodine at an ortho position thereof is provided, which does not require any step of recovery of iodine but can produce it at low cost, in high yield and with high quality. A phenol derivative is mixed with a pyridine and hydrogen peroxide or iodic acid as an oxidizing agent, and reacted with molecular iodine. As a result, iodination can be performed very efficiently with iodine in an amount close to the theoretical amount relative to the phenol derivative, and the 2-iodophenol or 2,6-diiodophenol derivative can be obtained in high yield and with high quality.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: A semiconductor integrated circuit device with a “PAD on I/O cell” structure in which a pad lead part is disposed almost in the center of an I/O part so as to reduce the chip layout area. In the I/O part, a transistor lies nearest to the periphery of the semiconductor chip. When seen in a plan view of the I/O part, a resistance lies above the transistor and a first and a second diode lie above the resistance; a second transistor lies above the diodes; and a logic block lies above the second transistor with a pad lead part, for example, formed in a metal wiring layer, therebetween. This permits the pad through the second transistor to be on the same node and therefore the pad lead part can be disposed almost in the center of the I/O part.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.

Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.

Abstract: When light is made incident to an optical waveguide path 14 formed through a main body 12 composed of silver (Ag) that is a plasmon active medium, surface plasmon is generated on a definition face 55 of the optical waveguide path 14 (including a fine aperture 16). Thus, the intensity of the light propagating in the optical waveguide path 14 is strengthened as the light propagates toward the fine aperture 16. In addition, a distal end 51 of a first protrusive piece 13a is more protrusive as compared with a distal end 52 of a second protrusive piece 13b. Thus, in a distal end part of a projection 13, the light is focused in the vicinity of the first protrusive piece 13a based on an intensity distribution of an electric field at the distal end part. Thus, the light having seeped out from the fine aperture 16 is restricted from spreading in a polarizing direction.

Abstract: To provide a semiconductor integrated circuit device advantageous against EM and ESD. A plurality of I/O cells; a power wire formed of a plurality of interconnect layers over the above-described I/O cells; a bonding pad formed in an upper layer of the power wire and in a position corresponding to the I/O cell; and lead-out areas capable of electrically coupling the I/O cell to the bonding pad are provided. The above-described power wire includes a first power wire and a second power wire, and the above-described I/O cell includes first elements coupled to the first power wire and second elements coupled to the second power wire. The first element is placed on the first power wire side, and the second element is placed on the second power wire side. The first power wire and the second power wire can allow for a high current due to the interconnect layers over the I/O cells, thus having robustness against EM and ESD.

Abstract: The invention provides a process for producing a chroman compound represented by formula (1), characterized in that the process includes allowing a phenol, an unsaturated compound, and a formaldehyde to react in the absence of catalyst and in the presence of water in an amount by mole 1 to 10 times that of the phenol. According to the present invention, a high-purity chroman compound can be produced in the absence of catalyst and under mild conditions. In addition, the invention provides an industrial means for producing the compound, without using a large amount of an acid or a base serving as a reaction promoter or a catalyst, which would otherwise cause side reactions, apparatus corrosion, etc.

Abstract: The present invention is provided to suppress occurrence of an erroneous operation in a protection circuit due to a relatively small power source fluctuation such as a power source noise. The protection circuit has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter whose input is connected between the first resistor and the capacitor, and a MOS transistor whose gate electrode receives an output of the inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

Abstract: A protection circuit with suppressed erroneous operation due to power source fluctuation has a first resistor and a capacitor connected in series between a power source line and a ground line, an inverter with an input connected between the first resistor and the capacitor, and a MOS transistor with a gate electrode that receives an output of the inverter and with a drain electrode and source electrode connected to the power source line and the ground line. When a high voltage fluctuation occurs in the power source line, a level change at a connection point between the first resistor and the capacitor is delayed according to a time constant. By the delay, the MOS transistor that receives an output of the inverter is temporarily turned on and discharges a high voltage to the ground line.

Abstract: When light is made incident to an optical waveguide path 14 formed through a main body 12 composed of silver (Ag) that is a plasmon active medium, surface plasmon is generated on a definition face 55 of the optical waveguide path 14 (including a fine aperture 16). Thus, the intensity of the light propagating in the optical waveguide path 14 is strengthened as the light propagates toward the fine aperture 16. In addition, a distal end 51 of a first protrusive piece 13a is more protrusive as compared with a distal end 52 of a second protrusive piece 13b. Thus, in a distal end part of a projection 13, the light is focused in the vicinity of the first protrusive piece 13a based on an intensity distribution of an electric field at the distal end part. Thus, the light having seeped out from the fine aperture 16 is restricted from spreading in a polarizing direction.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: A method of easily releasing a useful substance bonded to oligonucleotide without impairing a target nucleic acid; and a novel base therefore. A nucleoside of nucleotide (oligonucleotide containing thereof) represented by the formula (I) (wherein each of X and Y independently represents —O—, —NH—, —N(alkyl)- or —S—; R represents a functional unit, a reporter unit or a biofunctional molecule; each of R1 and R2 independently represents a hydrogen atom, a phosphate bond group, a phosphoramidite group or a nucleotide; and n is a numeral of 1 to 10). There is further provided a method of releasing the R group moiety at base portion by the use of the oligonucleotide comprising the nucleotide.

Abstract: A fuel cell-atmospheric-pressure turbine hybrid system uses the thermal energy of a cell exhaust gas discharged from an atmospheric-pressure, high-temperature fuel cell effectively, does not need any additional emergency protective device, and enables the use of lightweight, easy-to-process structural and piping materials to reduces the cost. The fuel cell-atmospheric-pressure turbine hybrid system includes: a combustor 2 for burning an exhaust gas G1 discharged from an atmospheric-pressure, high-temperature fuel cell 1; a turbine 3 in which a combustion gas G2 discharged from the combustor 2 expands and the pressure of the combustion gas G2 drops to a negative pressure; a compressor 4 for compressing an exhaust gas G3 discharged from the turbine 3 to increase the pressure of the exhaust gas G3; and a heat exchanger 5 for transferring heat from the high-temperature exhaust gas G3 discharged from the turbine 3 to low-temperature air A to be supplied to the fuel cell 1.

Abstract: In a method of removing conductive balls that are left on a mask provided on a substrate having pads thereon, the method includes: (a) making a sheet member close to the mask using a contacting mechanism such that a gap between the sheet member and the mask is set small than a diameter of the conductive balls. The conductive balls are removed in such a manner that the conductive balls are adhered onto the sheet member.

Abstract: A semiconductor integrated circuit device including an I/O circuitry capable of low-voltage high-speed operation at low cost is provided. In the I/O circuitry, when an I/O voltage (for example, 3.3 V) is lowered to a predetermined voltage (for example, 1.8 V), portions causing a speed deterioration are a level conversion unit and a pre-buffer unit for driving a main large-sized buffer. In view of this, a high voltage is applied to a level up converter and a pre-buffer circuit. By doing so, it is possible to achieve an I/O circuitry capable of low-voltage high-speed operation at low cost.

Abstract: The present invention has for its purpose to provide a technique capable of reducing planar dimension of the semiconductor device. An input/output circuit is formed over the semiconductor substrate, a grounding wiring and a power supply wiring pass over the input/output circuit, and a conductive layer for a bonding pad is formed thereover. The input/output circuit is formed of MISFET elements in the nMISFET forming region and the pMISFET forming region, resistance elements in the resistance element forming regions and diode elements in the diode element forming regions functioning as protective elements. A wiring connected to the protective elements and positioned under the grounding wiring and the power supply wiring is pulled out in a pulling-out region between the nMISFET forming region and the pMISFET forming region and between the grounding wiring and the power supply wiring to be connected to the conductive layer.