Patents by Inventor Kazushige Hotta

Kazushige Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11340310
    Abstract: This voltage imbalance assessment method is for a power conversion device comprising a forward converter for rectifying the voltage of a three-phase AC power supply, a smoothing capacitor for smoothing the rectified voltage, a detection unit for detecting the smoothed voltage, and a control unit. The control unit: uses the detected voltage to generate data indicating frequency components; compares, in the data indicating frequency components, the magnitude of the component that is four times the power supply frequency with the magnitude of the component that is six times the power supply frequency; and assesses the voltage imbalance of the three-phase AC power supply on the basis of the comparison.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 24, 2022
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Kazushige Hotta, Keisuke Tanabe, Yusuke Arao
  • Publication number: 20210075347
    Abstract: The purpose of the present invention is to provide a speed detection method for maintaining a fine time axis resolution and a power conversion device that uses the method. This power conversion device comprises an inverter for converting DC voltage into AC voltage and supplying the same to a motor, a motor speed calculation unit for calculating the speed of the motor from output pulses obtained from an encoder connected to the motor, and a control unit for receiving the motor speed from the motor speed calculation unit and controlling the inverter. In the power conversion device, the motor speed calculation unit measures the duty cycle of the output pulses, calculates the speed using the half cycles of the output pulses if the duty cycle is within a prescribed range from 50%, and calculates the speed using the full cycles of the output pulses if the duty ratio is outside of the prescribed range from 50%.
    Type: Application
    Filed: June 13, 2018
    Publication date: March 11, 2021
    Inventors: Hiroshi WATANABE, Masataka SASAKI, Masahiro HIRAGA, Yusuke ARAO, Atsuhiko NAKAMURA, Hiroyuki TOMITA, Kazushige HOTTA, Yusaku ONUMA
  • Patent number: 10903759
    Abstract: Provided is a power conversion device with which it is possible to acquire a sign of a system stop before the system stops, and to minimize the nonworking time of the system.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: January 26, 2021
    Assignee: Hitachi Industrial Equipment Systems Co., Ltd.
    Inventors: Yusuke Arao, Kazushige Hotta
  • Publication number: 20200400754
    Abstract: This voltage imbalance assessment method is for a power conversion device comprising a forward converter for rectifying the voltage of a three-phase AC power supply, a smoothing capacitor for smoothing the rectified voltage, a detection unit for detecting the smoothed voltage, and a control unit. The control unit: uses the detected voltage to generate data indicating frequency components; compares, in the data indicating frequency components, the magnitude of the component that is four times the power supply frequency with the magnitude of the component that is six times the power supply frequency; and assesses the voltage imbalance of the three-phase AC power supply on the basis of the comparison.
    Type: Application
    Filed: January 12, 2018
    Publication date: December 24, 2020
    Inventors: Kazushige HOTTA, Keisuke TANABE, Yusuke ARAO
  • Publication number: 20190173396
    Abstract: Provided is a power conversion device with which it is possible to acquire a sign of a system stop before the system stops, and to minimize the nonworking time of the system.
    Type: Application
    Filed: December 26, 2016
    Publication date: June 6, 2019
    Inventors: Yusuke ARAO, Kazushige HOTTA
  • Patent number: 8853701
    Abstract: In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device (100) is disclosed that is provided with a first P-type TFT (10a), a second P-type TFT (10b), a first N-type TFT (10c), and a second N-type TFT (10d), each having a channel region that is formed of polycrystalline silicon. When d1, d2, d3, and d4 respectively represent the concentrations of p-type impurities in the respective channel regions of the TFTs (10a to 10d), at least three values out of d1, d2, d3, and d4 are mutually different, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4.
    Type: Grant
    Filed: March 17, 2011
    Date of Patent: October 7, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Patent number: 8816437
    Abstract: Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: August 26, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masaki Yamanaka, Kazushige Hotta
  • Patent number: 8754418
    Abstract: Disclosed is a semiconductor device 100A that has first lightly doped drain regions 31A1 and 32A1 between a source region 34A1 and a channel region 33A1 of a first conductive-type driver circuit TFT 10A1 and/or between a drain region 35A1 and the channel region 33A1 of the first conductive-type driver circuit TFT 10A1, and second lightly doped drain regions 31C and 32C between a source region 34C and a channel region 33C of a first conductive-type pixel TFT 10C and/or between a drain region 35C and the channel region 33C of the first conductive-type pixel TFT 10C, in which the first lightly doped drain regions 31A1 and 32A1 have first conductive-type impurities n1 at a first impurity concentration C1, and the second lightly doped drain regions 31C and 32C have first conductive-type impurities n1 at the first impurity concentration C1 and second conductive-type impurities p2 at a second impurity concentration C2.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: June 17, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20130175535
    Abstract: In order to efficiently manufacture a semiconductor device having a plurality of TFTs formed thereon, which can be applied to a variety of uses, a semiconductor device (100) is disclosed that is provided with a first P-type TFT (10a), a second P-type TFT (10b), a first N-type TFT (10c), and a second N-type TFT (10d), each having a channel region that is formed of polycrystalline silicon. When d1, d2, d3, and d4 respectively represent the concentrations of p-type impurities in the respective channel regions of the TFTs (10a to 10d), at least three values out of d1, d2, d3, and d4 are mutually different, and d1, d2, d3, and d4 satisfy relations of d1<d2 and d3<d4.
    Type: Application
    Filed: March 17, 2011
    Publication date: July 11, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kazushige Hotta
  • Publication number: 20130146879
    Abstract: Disclosed is a semiconductor device in which an n-channel type first thin film transistor and a p-channel type second thin film transistor are provided on the same substrate. The first thin film transistor has a first semiconductor layer (11), and the second thin film transistor has a second semiconductor layer (20), a third semiconductor layer (21), and a fourth semiconductor layer (22). The first semiconductor layer (11), the second semiconductor layer (20), the third semiconductor layer (21) and the fourth semiconductor layer (22) are formed of the same film, and the first and second semiconductor layers (11, 20) respectively have slanted portions (11e, 20e) positioned at respective peripheries, and main portions (11m, 20m) made of portions other than the slanted portions.
    Type: Application
    Filed: June 13, 2011
    Publication date: June 13, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Masaki Yamanaka, Kazushige Hotta
  • Publication number: 20130078787
    Abstract: Disclosed is a method for manufacturing a semiconductor device, including the steps of: forming a first semiconductor film (2) and a second semiconductor film (4) over a glass substrate (6); forming a photosensitive resin over the glass substrate (6) to cover the first semiconductor film (2) and the second semiconductor film (4); conducting an exposure process in which controlled amounts of exposure radiation are projected to the photosensitive resin using a photomask; conducting a developing process on the photosensitive resin that was subjected to the exposure process, to form a first resist (40) over the first semiconductor film (2) and to form a second resist (41) over the second semiconductor film (4); implanting an n-type impurity into the first semiconductor film (2) using the first resist (40) and the second resist (41) as masks; and removing the first resist (40) and implanting a p-type impurity into the first semiconductor film (2) using the second resist (41) as a mask.
    Type: Application
    Filed: May 16, 2011
    Publication date: March 28, 2013
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Hiroshi Nakatsuji, Kazushige Hotta, Naoki Makita
  • Publication number: 20130056766
    Abstract: Disclosed is a semiconductor device 100A that has first lightly doped drain regions 31A1 and 32A1 between a source region 34A1 and a channel region 33A1 of a first conductive-type driver circuit TFT 10A1 and/or between a drain region 35A1 and the channel region 33A1 of the first conductive-type driver circuit TFT 10A1, and second lightly doped drain regions 31C and 32C between a source region 34C and a channel region 33C of a first conductive-type pixel TFT 10C and/or between a drain region 35C and the channel region 33C of the first conductive-type pixel TFT 10C, in which the first lightly doped drain regions 31A1 and 32A1 have first conductive-type impurities n1 at a first impurity concentration C1, and the second lightly doped drain regions 31C and 32C have first conductive-type impurities n1 at the first impurity concentration C1 and second conductive-type impurities p2 at a second impurity concentration C2.
    Type: Application
    Filed: February 2, 2011
    Publication date: March 7, 2013
    Applicant: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20100327353
    Abstract: A gate electrode 14 of a thin film transistor 100 included in a semiconductor device of the present invention is constituted of a single conductive film. A semiconductor layer 10 includes a first lightly doped impurity region which is provided between the channel region 12 and the source region 15 and which has a lower impurity concentration than those of the source and drain regions 15, and a second lightly doped impurity region which is provided between the channel region 12 and the drain region 15 and which has a lower impurity concentration than those of the source and drain regions 15. The entirety of one of the first and second lightly doped impurity regions (region 16a) extends under the gate electrode, and the other of the first and second lightly doped impurity regions (region 16b) does not extend under the gate electrode.
    Type: Application
    Filed: January 20, 2009
    Publication date: December 30, 2010
    Inventors: Atsushi Shoji, Isao Nakanishi, Kazushige Hotta
  • Patent number: 7859078
    Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: December 28, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Patent number: 7808570
    Abstract: An active matrix substrate has: scanning lines extending in row direction and image data lines extending in column direction, formed in display area; semiconductor islands at each cross point and in peripheral circuit area; a first gate insulating film formed on each pixel semiconductor island; a first gate made of a first wiring layer and formed on said first gate insulating film; a second gate insulating film thinner than the first gate insulating film formed on peripheral circuit semiconductor island; and a second gate electrode made of a second wiring layer and formed on the second gate insulating film, wherein the pixel transistor semiconductor island, first gate insulating film and first gate electrode constitute a pixel transistor, and the scanning line includes a lower layer made of the second wiring line and an upper layer made of the first wiring line connected to the lower layer.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: October 5, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kazushige Hotta, Takuya Watanabe, Noriyuki Ohashi
  • Patent number: 7700495
    Abstract: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: April 20, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Seiji Doi, Kazushige Hotta, Takuya Hirano, Kenichi Yanai
  • Patent number: 7619288
    Abstract: A method for manufacturing a thin film transistor substrate includes a step of forming a plurality of island-like semiconductor films above an insulating transparent substrate; a step of forming a gate insulating film on each of the island-like semiconductor films; a step of forming first conductivity type LDD regions on both sides in the first island-like semiconductor film by leaving a channel region and forming a first conductivity type normally-on channel region having an impurity density equivalent to that of the LDD region in the second island-like semiconductor film; a step of forming a first gate electrode partially covering the LDD region and forming a second gate electrode above the normally-on channel region, and a step of forming a first conductivity type source/drain region having an impurity density higher than that of the LDD region in regions on the both sides of the gate electrode.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: November 17, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20090224251
    Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.
    Type: Application
    Filed: March 30, 2009
    Publication date: September 10, 2009
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kazushige Hotta
  • Patent number: 7535065
    Abstract: A first insulating film is formed. Then, a gate electrode of a low voltage drive thin film transistor and a mask film for covering a region constituting a channel of a high voltage drive thin film transistor are formed with a molybdenum film on the first insulating film. An impurity is implanted into a semiconductor film while using the gate electrode and the mask film as a mask, thereby forming a high density impurity region. Thereafter, the impurity is activated by performing a thermal process under a condition at 500° C. and for 2 hours, for example. Subsequently, the mask film is removed and a second insulating film is formed. A gate electrode of the high voltage drive thin film transistor is formed with an aluminum alloy on the second insulating film.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: May 19, 2009
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Kazushige Hotta
  • Publication number: 20080283840
    Abstract: The present invention relates to a thin film transistor device formed on an insulating substrate of a liquid crystal display device and others, a method of manufacturing the same, and a liquid crystal display device. In structure, there are provided the steps of forming a negative photoresist film on a first insulating film for covering a first island-like semiconductor film, forming a resist mask that has an opening portion in an inner region with respect to a periphery of the first island-like semiconductor film by exposing/developing the negative photoresist film from a back surface side of a transparent substrate, etching the first insulating film in the opening portion of the resist mask, forming a second insulating film for covering the first insulating film and a conductive film thereon, and forming a first gate electrode and a second gate electrode by patterning the conductive film.
    Type: Application
    Filed: February 11, 2008
    Publication date: November 20, 2008
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Seiji Doi, Kazushige Hotta, Takuya Hirano, Kenichi Yanai