Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.

Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.

Abstract: A semiconductor device according to the present invention includes a substrate having a cell portion and a terminal portion surrounding the cell portion, a surface structure provided on the substrate, and a back surface electrode provided on the back surface of the substrate, the surface structure includes a convex portion protruding upward above the cell portion, and at least a part of the cell portion is thinner than the terminal portion.

Abstract: A wound wire is wound around a core assembly so that both ends are short-circuited. In a coupling pin insertion state in which a coupling pin is inserted in a through hole of the core assembly, outer-peripheral space parts of respective divided core portions of the core assembly are disposed so as to overlap in plan view. Consequently, an air gap is formed in a part of a side surface of the core assembly. Before formation of a covering member, a main wire is caused to pass through the air gap and is thus disposed in a wiring hole of the core assembly. Then, the covering member for closing the air gap is provided on an outer peripheral surface side of the core assembly including the air gap so that a core structure is obtained.

Abstract: A wound wire is wound around a core assembly so that both ends are short-circuited. In a coupling pin insertion state in which a coupling pin is inserted in a through hole of the core assembly, outer-peripheral space parts of respective divided core portions of the core assembly are disposed so as to overlap in plan view. Consequently, an air gap is formed in a part of a side surface of the core assembly. Before formation of a covering member, a main wire is caused to pass through the air gap and is thus disposed in a wiring hole of the core assembly. Then, the covering member for closing the air gap is provided on an outer peripheral surface side of the core assembly including the air gap so that a core structure is obtained.

Abstract: A switching chip using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink, an insulating substrate and a conductive plate, with a first conductive layer sandwiched in between. Further, a diode chip having a smaller area than a cathode electrode and using a wide gap semiconductor as the base material is located on the cathode electrode which has a smaller area than an anode electrode, with a second conductive layer sandwiched in between. A closed container encloses every structural component except an exposed portion of a bottom surface in the interior space.

Abstract: A switching chip using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink, an insulating substrate and a conductive plate, with a first conductive layer sandwiched in between. Further, a diode chip having a smaller area than a cathode electrode and using a wide gap semiconductor as the base material is located on the cathode electrode which has a smaller area than an anode electrode, with a second conductive layer sandwiched in between. A closed container encloses every structural component except an exposed portion of a bottom surface in the interior space.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.

Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.

Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.