Patents by Inventor Kazushige Toriyama
Kazushige Toriyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424510Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: GrantFiled: August 7, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Patent number: 10388566Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: GrantFiled: March 11, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Patent number: 10252363Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.Type: GrantFiled: January 10, 2017Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Hiroyuki Mori, Yasumitsu Orii, Kazushige Toriyama, Ting-Li Yang
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Patent number: 10141278Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: GrantFiled: November 6, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama
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Patent number: 10090586Abstract: A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor.Type: GrantFiled: July 10, 2017Date of Patent: October 2, 2018Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Noam Kaminski, Keishi Okamoto, Kazushige Toriyama
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Patent number: 9941230Abstract: The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.Type: GrantFiled: December 30, 2015Date of Patent: April 10, 2018Assignee: International Business Machines CorporationInventors: Keiji Matsumoto, Keishi Okamoto, Yasumitsu K. Orii, Kazushige Toriyama
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Publication number: 20180076162Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: ApplicationFiled: November 6, 2017Publication date: March 15, 2018Inventors: Akihiro HORIBE, Keiji MATSUMOTO, Keishi OKAMOTO, Kazushige TORIYAMA
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Patent number: 9893031Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: GrantFiled: September 2, 2016Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama
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Publication number: 20170338152Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: ApplicationFiled: August 7, 2017Publication date: November 23, 2017Inventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Publication number: 20170309998Abstract: A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor.Type: ApplicationFiled: July 10, 2017Publication date: October 26, 2017Inventors: Toyohiro Aoki, Noam Kaminski, Keishi Okamoto, Kazushige Toriyama
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Patent number: 9780442Abstract: A joined structure which is configured such that a space between adjacent substrates is filled with a filling material. The joined structure includes a first substrate having a first conductor formed on a surface of the first substrate, a second substrate having a second conductor formed on a surface of the second substrate, arranged so that a surface of the first substrate faces a surface of the second substrate, a connecting conductor which electrically connects the first conductor and the second conductor, and a filling material between the first substrate and the second substrate. The filling material is formed into such a shape that a space is provided which corresponds to at least one of the first conductor, the second and the connecting conductor.Type: GrantFiled: June 10, 2015Date of Patent: October 3, 2017Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Noam Kaminski, Keishi Okamoto, Kazushige Toriyama
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Patent number: 9772462Abstract: A structure is formed which is prepared as a via for electrical contact passing through layers of an optical waveguide, in a multilayer structure including an electrical substrate and the laminated layers of the optical waveguide. The surface of an electrode pad is plated with solder. The layers of the optical waveguide are formed above the portion plated with solder are removed to expose the portion plated with solder. A device is prepared having both a light-emitter or photoreceptor in optical contact with the optical waveguide, and a stud (pillar). The stud (pillar) is inserted into the portion in which layers of the optical waveguide have been removed, and the plated solder is melted to bond the electrode pad on top of the electrical substrate to the tip of the inserted stud (pillar).Type: GrantFiled: April 28, 2016Date of Patent: September 26, 2017Assignee: International Business Machines CorporationInventors: Hirokazu Noma, Keishi Okamoto, Masao Tokunari, Kazushige Toriyama, Yutaka Tsukada
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Publication number: 20170263498Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Publication number: 20170194277Abstract: The present invention provides an electrical connecting structure between a substrate 21 and a semiconductor chip 22. The electrical connecting structure comprises a metal bump 26 formed on a contact pad 28 of a semiconductor chip 22 and a coating layer 25 formed on the metal bump 26 of the semiconductor chip 22. The coating layer includes material not wettable with solder. The electrical connecting structure further comprises a metal pad 24 formed on the substrate 21. The electrical connecting structure further comprises a solder 29 connecting to a side surface of the metal bump 26 and an outer surface of the metal pad 24. The outer surface is not covered by the coating layer 25.Type: ApplicationFiled: December 30, 2015Publication date: July 6, 2017Inventors: Keji Matsumodo, Keishi Okamoto, Yasumitsu K. Orii, Kazushige Toriyama
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Patent number: 9698119Abstract: A method of forming a structure for an interfacial alloy layer which is able to improve the electromigration (EM) resistance of a solder joint. More specifically, in this structure, a controlled interfacial alloy layer is provided on both sides of a solder joint. In order to form this structure, aging (maintenance of high-temperature conditions) is performed until an interfacial alloy layer of Cu3Sn has a thickness of at least 1.5 ?m.Type: GrantFiled: May 19, 2016Date of Patent: July 4, 2017Assignee: International Business Machines CorporationInventors: Hirokazu Noma, Yasumitsu Orii, Kazushige Toriyama
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Publication number: 20170120361Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.Type: ApplicationFiled: January 10, 2017Publication date: May 4, 2017Inventors: Toyohiro Aoki, Akihiro Horibe, Hiroyuki Mori, Yasumitsu Orii, Kazushige Toriyama, Ting-Li Yang
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Patent number: 9586281Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.Type: GrantFiled: August 21, 2015Date of Patent: March 7, 2017Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Hiroyuki Mori, Yasumitsu Orii, Kazushige Toriyama, Ting-Li Yang
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Publication number: 20170005053Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: ApplicationFiled: September 2, 2016Publication date: January 5, 2017Inventors: Akihiro HORIBE, Keiji MATSUMOTO, Keishi OKAMOTO, Kazushige TORIYAMA
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Patent number: 9520375Abstract: A method of forming a solder bump on a substrate includes: forming a conductive layer(s) on the substrate having a surface on which an electrode pad is prepared; forming a resist layer on the conductive layer(s) having an opening over the electrode pad; forming a metal pillar in the opening of the resist layer, wherein the metal pillar includes a first conductive material; forming a space between sidewalls of the resist layer and the metal pillar; forming a metal barrier layer in the space and on a top surface of the metal pillar, the metal barrier layer including a second conductive material that is different from the first conductive material of the metal pillar; forming a solder layer on the metal barrier layer over the top surface of the metal pillar; removing the resist layer; removing the conductive layer(s); and forming the solder bump by reflowing the solder layer.Type: GrantFiled: April 30, 2015Date of Patent: December 13, 2016Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Hiroyuki Mori, Yasumitsu K. Orii, Kazushige Toriyama, Shintaro Yamamichi
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Patent number: 9508594Abstract: A substrate bonding method is able to reliably bond substrates while avoiding a reduction in yield made worse by finer pitches. The substrate bonding method can include: forming an adhesive resin layer on a surface of a first substrate on which a pad has been formed; forming an opening on the adhesive resin layer above the pad; filling the opening with molten solder to form a pillar-shaped solder bump; and applying heat and pressure to the first substrate and a second substrate while a terminal formed on the second substrate is aligned with the solder bump.Type: GrantFiled: November 3, 2015Date of Patent: November 29, 2016Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Hiroyuki Mori, Kazushige Toriyama