Patents by Inventor Kazutaka Ishigo

Kazutaka Ishigo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9941177
    Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kentaro Kasa, Kazuya Fukuhara, Kazutaka Ishigo, Manabu Takakuwa, Yoshinori Hagio, Kazuhiro Segawa, Yuki Murasaka, Tetsuya Kugimiya, Yuu Yamayose, Yosuke Okamoto
  • Publication number: 20170271214
    Abstract: A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate disposed on the stage, an optical pattern detection unit that detects a position of a pattern on the substrate, and a processing unit that corrects the detected pattern position based on the measured shape of the substrate.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 21, 2017
    Inventors: Kentaro KASA, Kazuya FUKUHARA, Kazutaka ISHIGO, Manabu TAKAKUWA, Yoshinori HAGIO, Kazuhiro SEGAWA, Yuki MURASAKA, Tetsuya KUGIMIYA, Yuu YAMAYOSE, Yosuke OKAMOTO
  • Patent number: 9250542
    Abstract: According to one embodiment, a method includes preliminarily measuring the amount of overlay or alignment shift of the mark for overlay or alignment measurement while sequentially shifting a position of a measurement area relative to the mark for overlay or alignment measurement so as to position the mark for overlay or alignment measurement on each of a plurality of partial areas. The measurement area corresponds to a field angle of the optical measurement system, and an inside of the measurement area is two-dimensionally divided into the partial areas. The method includes calculating a tool-induced shift regarding a characteristic deviation of the optical measurement system for each of the plurality of partial areas based on a preliminarily measured result of the amount of overlay or alignment shift. The method includes determining a partial area to be used from among the plurality of partial areas on the basis of the tool-induced shift calculated for each of the plurality of partial areas.
    Type: Grant
    Filed: March 18, 2011
    Date of Patent: February 2, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Ishigo
  • Patent number: 9158212
    Abstract: According to one embodiment, there is provided an exposure apparatus including an acquisition unit, and a calculation unit. The acquisition unit obtains a plurality of measured values. The plurality of measured values is measured for a plurality of focus offset quantities different from each other. Each of the plurality of measured values represents positional deviation distribution within a shot area. The calculation unit calculates a plurality of distortion errors from the plurality of measured values and obtains a correlation between the focus offset quantity and alignment compensation value to compensate for the distortion error, in response to the plurality of focus offset quantities and the plurality of distortion errors.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 13, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Ishigo
  • Publication number: 20140285787
    Abstract: According to one embodiment, an exposure system includes: a supporting stage; a plurality of masks provided on an upper side of the supporting stage; and a light source being capable of irradiating a substrate with light through the plurality of masks, the plurality of masks including: a first mask, and a light shielding film being patterned in the first mask; and a second mask provided on an upper side or a lower side of the first mask, the second mask including a second region facing a first region of the first mask, the light shielding film not being present in the first region, and a light shielding film not being patterned in the second region or the light shielding film being patterned in at least a part of the second region, and a plurality of laser-irradiated marks being provided in at least the second region of the second mask.
    Type: Application
    Filed: August 29, 2013
    Publication date: September 25, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Eiji YONEDA, Nobuhiro Komine, Satomi Higashibata, Kazutaka Ishigo, Yosuke Okamoto
  • Patent number: 8790851
    Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Okamoto, Kazutaka Ishigo, Taketo Kuriyama
  • Publication number: 20130252429
    Abstract: A photo mask for exposing according to an embodiment includes a mark pattern arranged in a mark region that is different from an effective region to form a semiconductor device; and a regular pattern arranged in the mark region and around the mark pattern and smaller than the mark pattern in size and pitch.
    Type: Application
    Filed: August 8, 2012
    Publication date: September 26, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke OKAMOTO, Kazutaka ISHIGO, Taketo KURIYAMA
  • Publication number: 20130222777
    Abstract: According to one embodiment, there is provided an exposure apparatus including an acquisition unit, and a calculation unit. The acquisition unit obtains a plurality of measured values. The plurality of measured values is measured for a plurality of focus offset quantities different from each other. Each of the plurality of measured values represents positional deviation distribution within a shot area. The calculation unit calculates a plurality of distortion errors from the plurality of measured values and obtains a correlation between the focus offset quantity and alignment compensation value to compensate for the distortion error, in response to the plurality of focus offset quantities and the plurality of distortion errors.
    Type: Application
    Filed: August 31, 2012
    Publication date: August 29, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka ISHIGO
  • Patent number: 8364437
    Abstract: A method of inspecting a mark arrangement according to an embodiment of the present invention includes: generating mask data in which mark seed data that includes an inspection mark that includes vector information and is not drawn on a mask and mark data is arranged on a scribe line of the mask, calculating coordinates of the inspection mark from a reference position of the mark seed data, detecting an arrangement state of the inspection mark with respect to the reference position by using the coordinates and vector information, and judging whether the mark seed data is correctly arranged by comparing the arrangement state of the inspection mark with an arrangement check rule.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: January 29, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Morinaga, Kazutaka Ishigo, Takaki Kumanomido
  • Publication number: 20120069337
    Abstract: According to one embodiment, a method includes preliminarily measuring the amount of overlay or alignment shift of the mark for overlay or alignment measurement while sequentially shifting a position of a measurement area relative to the mark for overlay or alignment measurement so as to position the mark for overlay or alignment measurement on each of a plurality of partial areas. The measurement area corresponds to a field angle of the optical measurement system, and an inside of the measurement area is two-dimensionally divided into the partial areas. The method includes calculating a tool-induced shift regarding a characteristic deviation of the optical measurement system for each of the plurality of partial areas based on a preliminarily measured result of the amount of overlay or alignment shift. The method includes determining a partial area to be used from among the plurality of partial areas on the basis of the tool-induced shift calculated for each of the plurality of partial areas.
    Type: Application
    Filed: March 18, 2011
    Publication date: March 22, 2012
    Inventor: Kazutaka ISHIGO
  • Patent number: 8072601
    Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Fukuhara, Kazutaka Ishigo
  • Patent number: 8034515
    Abstract: A pattern designing method according to an embodiment of the present invention includes: designing a first pattern for inspection formed by arraying a plurality of first mark rows, in which rectangular marks are arrayed at predetermined intervals in a first direction, in a second direction perpendicular to the first direction and designing a second pattern for inspection formed by arraying, in the second direction, a plurality of second mark rows in which rectangular marks are arranged among the marks arrayed in the first direction of the first mark row and a forming position in the second direction is arranged to overlap the first mark row by predetermined overlapping length.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: October 11, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Ishigo
  • Patent number: 7973419
    Abstract: According to an aspect of the invention, there is provided a semiconductor device including a semiconductor substrate, a p-type impurity diffusion layer formed on the semiconductor substrate, and Ni silicide formed on the diffusion layer, wherein an alignment mark for lithography is formed on the Ni silicide.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: July 5, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoyasu Kudo, Kazutaka Ishigo
  • Patent number: 7906258
    Abstract: In a photomask in which a device pattern, an alignment mark and a superimposition inspection mark are formed on a light transmitting base, each of the alignment mark and the superimposition inspection mark includes a main mark portion, and first and second auxiliary pattern portions. The main mark portion is constituted of one of a space pattern and a line pattern, the pattern having a linear width to be resolved on a photosensitive film formed on a semiconductor wafer, and each of the first and second auxiliary pattern portions includes an auxiliary pattern constituted of one of a repeated pattern of a space pattern and a repeated pattern of a line pattern, the repeated pattern having a linear width not to be resolved on the photosensitive film. The pitch of the repeated pattern is equal to the minimum pitch of the device pattern.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuhiro Komine, Kazutaka Ishigo, Noriaki Sasaki, Masayuki Hatano
  • Publication number: 20100291477
    Abstract: A pattern designing method according to an embodiment of the present invention includes: designing a first pattern for inspection formed by arraying a plurality of first mark rows, in which rectangular marks are arrayed at predetermined intervals in a first direction, in a second direction perpendicular to the first direction and designing a second pattern for inspection formed by arraying, in the second direction, a plurality of second mark rows in which rectangular marks are arranged among the marks arrayed in the first direction of the first mark row and a forming position in the second direction is arranged to overlap the first mark row by predetermined overlapping length.
    Type: Application
    Filed: September 10, 2009
    Publication date: November 18, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka ISHIGO
  • Publication number: 20100211352
    Abstract: A method of inspecting a mark arrangement according to an embodiment of the present invention includes: generating mask data in which mark seed data that includes an inspection mark that includes vector information and is not drawn on a mask and mark data is arranged on a scribe line of the mask, calculating coordinates of the inspection mark from a reference position of the mark seed data, detecting an arrangement state of the inspection mark with respect to the reference position by using the coordinates and vector information, and judging whether the mark seed data is correctly arranged by comparing the arrangement state of the inspection mark with an arrangement check rule.
    Type: Application
    Filed: December 30, 2009
    Publication date: August 19, 2010
    Inventors: Hiroyuki MORINAGA, Kazutaka Ishigo, Takaki Kumanomido
  • Publication number: 20090246709
    Abstract: A manufacturing method of a semiconductor device includes preparing a first circuit pattern original plate including a first pattern part of a mark pattern, preparing a second circuit pattern original plate including a second pattern part of the mark pattern, transferring the first pattern part to a mask film on an underlying area to form a first transfer pattern part in the mask film, transferring the second pattern part to the mask film to form a second transfer pattern part in the mask film, and patterning the underlying area by using the mask film including a transfer mark pattern, which is obtained by combining the first transfer pattern part and the second transfer pattern part, as a mask to form an underlying mark pattern in the underlying area.
    Type: Application
    Filed: March 19, 2009
    Publication date: October 1, 2009
    Inventors: Tetsuro NAKASUGI, Takashi SATO, Kazutaka ISHIGO
  • Publication number: 20080248431
    Abstract: A pattern forming method includes forming a first anti-reflection coating on a substrate, the substrate having an uneven surface; forming a second anti-reflection coating on the first anti-reflection coating, the first anti-reflection coating having an uneven surface, and the second anti-reflection coating planarizing the uneven surface of the first anti-reflection coating; forming an intermediate layer film on the second anti-reflection coating; forming a resist film on the intermediate-layer film; patterning the resist film to form a resist pattern; forming an intermediate-layer pattern by etching the intermediate-layer film using the resist pattern as a mask; and forming an under-layer pattern by etching the first and second anti-reflection coatings using the intermediate-layer pattern as a mask.
    Type: Application
    Filed: November 21, 2007
    Publication date: October 9, 2008
    Inventors: Yuriko Seino, Seiro Myoshi, Kazutaka Ishigo
  • Publication number: 20080225254
    Abstract: In a photomask in which a device pattern, an alignment mark and a superimposition inspection mark are formed on a light transmitting base, each of the alignment mark and the superimposition inspection mark includes a main mark portion, and first and second auxiliary pattern portions. The main mark portion is constituted of one of a space pattern and a line pattern, the pattern having a linear width to be resolved on a photosensitive film formed on a semiconductor wafer, and each of the first and second auxiliary pattern portions includes an auxiliary pattern constituted of one of a repeated pattern of a space pattern and a repeated pattern of a line pattern, the repeated pattern having a linear width not to be resolved on the photosensitive film. The pitch of the repeated pattern is equal to the minimum pitch of the device pattern.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 18, 2008
    Inventors: Nobuhiro KOMINE, Kazutaka Ishigo, Noriaki Sasaki, Masayuki Hatano
  • Publication number: 20080206898
    Abstract: A method of forming a monitor mark includes forming an insulating film on a semiconductor substrate, and forming a first repetitive line pattern group and a second repetitive line pattern group by patterning the insulating film on the semiconductor substrate, such that the first repetitive line pattern group and the second repetitive line pattern group face each other with a predetermined space therebetween.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Inventors: Kazuya FUKUHARA, Kazutaka Ishigo