Patents by Inventor Kazutaka Kobayashi
Kazutaka Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12071370Abstract: The present invention relates to a glass substrate including a pair of main surfaces and an end surface, and having a surface layer diffusion Sn atom concentration of 2.0×1018 atomic/cm3 or more and 1.4×1019 atomic/cm3 or less in at least one of the main surfaces, the surface layer diffusion Sn atom concentration being obtained by subtracting an Sn atom concentration of an inside of the glass substrate from an Sn atom concentration of a surface layer of the glass substrate, in which the Sn atom concentration of a surface layer of the glass substrate is defined as an Sn atom concentration at a depth of 0.1 to 0.3 ?m from the main surface and the Sn atom concentration of an inside of the glass substrate is defined as an Sn atom concentration at a depth of 9.0 to 9.2 ?m from the main surface.Type: GrantFiled: January 28, 2021Date of Patent: August 27, 2024Assignee: AGC Inc.Inventors: Hirofumi Tokunaga, Daisuke Kobayashi, Kazutaka Ono, Atsuyoshi Takenaka, Yoshitaka Maeyanagi
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Publication number: 20230410733Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that are able to provide suitable functionality according to applications. The signal processing apparatus provided by the present technology includes a signal processing section that acquires at least one of first information regarding a color of a video to be displayed on a panel section, second information regarding brightness of a screen of the panel section, and third information measured as a physical quantity related to the panel section, and that performs, on the basis of the acquired information, adaptive control of a voltage according to a load on and an application of the panel section. The voltage is used for driving the panel section. The present technology is applicable, for example, to a self-luminous display apparatus.Type: ApplicationFiled: August 31, 2023Publication date: December 21, 2023Applicant: Sony Group CorporationInventors: Masao Zen, Tetsuo Ikeyama, Daisuke Miki, Syunsuke Kikuchi, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida, Masayoshi Sasaki, Masayuki Okochi
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Publication number: 20230402003Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that may reduce the effect of deterioration in element of a display panel. Provided is a signal processing apparatus including a signal processing unit configured to acquire, in changing a video signal from a low luminance display signal to a high luminance display signal by luminance enhancement, an accumulated load increase amount obtained by measuring and accumulating amounts of increase in load on a display panel caused by luminance enhancement, and adaptively control, in reference to the accumulated load increase amount acquired, a first gain for improving luminance of the video signal, according to a degree of effect of deterioration in element of the display panel. The present technology is applicable to self-luminous display apparatuses, for example.Type: ApplicationFiled: August 28, 2023Publication date: December 14, 2023Applicant: Sony Group CorporationInventors: Masao Zen, Syunsuke Kikuchi, Daisuke Miki, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida
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Patent number: 11817048Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that are able to provide suitable functionality according to applications. The signal processing apparatus provided by the present technology includes a signal processing section that acquires at least one of first information regarding a color of a video to be displayed on a panel section, second information regarding brightness of a screen of the panel section, and third information measured as a physical quantity related to the panel section, and that performs, on the basis of the acquired information, adaptive control of a voltage according to a load on and an application of the panel section. The voltage is used for driving the panel section. The present technology is applicable, for example, to a self-luminous display apparatus.Type: GrantFiled: April 19, 2021Date of Patent: November 14, 2023Inventors: Masao Zen, Tetsuo Ikeyama, Daisuke Miki, Syunsuke Kikuchi, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida, Masayoshi Sasaki, Masayuki Okochi
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Patent number: 11790843Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that may reduce the effect of deterioration in element of a display panel. Provided is a signal processing apparatus including a signal processing unit configured to acquire, in changing a video signal from a low luminance display signal to a high luminance display signal by luminance enhancement, an accumulated load increase amount obtained by measuring and accumulating amounts of increase in load on a display panel caused by luminance enhancement, and adaptively control, in reference to the accumulated load increase amount acquired, a first gain for improving luminance of the video signal, according to a degree of effect of deterioration in element of the display panel. The present technology is applicable to self-luminous display apparatuses, for example.Type: GrantFiled: April 19, 2021Date of Patent: October 17, 2023Inventors: Masao Zen, Syunsuke Kikuchi, Daisuke Miki, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida
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Publication number: 20230140888Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that may reduce the effect of deterioration in element of a display panel. Provided is a signal processing apparatus including a signal processing unit configured to acquire, in changing a video signal from a low luminance display signal to a high luminance display signal by luminance enhancement, an accumulated load increase amount obtained by measuring and accumulating amounts of increase in load on a display panel caused by luminance enhancement, and adaptively control, in reference to the accumulated load increase amount acquired, a first gain for improving luminance of the video signal, according to a degree of effect of deterioration in element of the display panel. The present technology is applicable to self-luminous display apparatuses, for example.Type: ApplicationFiled: April 19, 2021Publication date: May 11, 2023Applicant: Sony Group CorporationInventors: Masao Zen, Syunsuke Kikuchi, Daisuke Miki, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida
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Publication number: 20230125418Abstract: The present technology relates to a signal processing apparatus, a signal processing method, and a display apparatus that are able to provide suitable functionality according to applications. The signal processing apparatus provided by the present technology includes a signal processing section that acquires at least one of first information regarding a color of a video to be displayed on a panel section, second information regarding brightness of a screen of the panel section, and third information measured as a physical quantity related to the panel section, and that performs, on the basis of the acquired information, adaptive control of a voltage according to a load on and an application of the panel section. The voltage is used for driving the panel section. The present technology is applicable, for example, to a self-luminous display apparatus.Type: ApplicationFiled: April 19, 2021Publication date: April 27, 2023Applicant: Sony Group CorporationInventors: Masao Zen, Tetsuo Ikeyama, Daisuke Miki, Syunsuke Kikuchi, Kazuhiro Nukiyama, Kazutaka Kobayashi, Yasushi Konuma, Kazuki Uchida, Masayoshi Sasaki, Masayuki Okochi
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Patent number: 10128139Abstract: A substrate holding method is to horizontally hold a substrate, and includes a positioning step of positioning a substrate by moving a substrate transfer mechanism and by allowing the peripheral edge of the substrate to come into contact with the plurality of positioning pins, a substrate grasping step of bringing the plurality of grasping pins into a closed state after completing the positioning step so that the substrate held by the plurality of positioning pins and the plurality of grasping pins, and a transfer mechanism receding step of allowing the substrate transfer mechanism to recede from above the spin base after completing the substrate grasping step.Type: GrantFiled: March 25, 2016Date of Patent: November 13, 2018Assignee: SCREEN Holdings Co., Ltd.Inventors: Kazutaka Kobayashi, Hiroshi Kato
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Patent number: 9837337Abstract: A wiring substrate includes an electronic component mounting pad, an electrode pad arranged at an outer side of the electronic component mounting pad, a first insulation layer formed on the electronic component mounting pad and the electrode pad, an opening formed in the first insulation layer on the electronic component mounting pad, a connection hole formed in the first insulation layer on the electrode pad, and recess portions formed at the electronic component mounting pad in the opening and at the electrode pad in the connection hole, respectively.Type: GrantFiled: November 24, 2015Date of Patent: December 5, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kazutaka Kobayashi
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Patent number: 9685391Abstract: A wiring board includes a substrate having first and second opposite surfaces, a first adhesive layer on the first surface of the substrate, a thermal diffusion metal pattern on the first adhesive layer, multiple vias vertically extending from the thermal diffusion metal pattern into the substrate through the first adhesive layer with a gap around each of the vias in the substrate and the first adhesive layer, and a second adhesive layer on the second surface of the substrate. The thermal diffusion metal pattern is not to be electrically connected to a semiconductor device to be mounted. The second adhesive layer fills in the gap around each of the vias within the substrate and the first adhesive layer. The gap includes a first gap and a second gap in the substrate and the first adhesive layer, respectively. The second gap is greater in lateral size than the first gap.Type: GrantFiled: April 5, 2016Date of Patent: June 20, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kazutaka Kobayashi
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Patent number: 9655238Abstract: A wiring board includes a heat dissipation plate, a heat-conductive adhesive layer, an insulating layer, a thermal via, a heat dissipation metal terminal, and electrodes. The heat-conductive adhesive layer is disposed on the heat dissipation plate. The insulating layer is disposed on the heat-conductive adhesive layer. The insulating layer is formed with an opening portion. The thermal via is disposed in the opening portion of the insulating layer. The heat dissipation metal terminal is disposed on the thermal via and electrically connected to the heat dissipation plate. The electrodes are disposed on the insulating layer. The electrodes are to be connected to an electronic component.Type: GrantFiled: April 28, 2015Date of Patent: May 16, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kazutaka Kobayashi
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Publication number: 20160307814Abstract: A wiring board includes a substrate having first and second opposite surfaces, a first adhesive layer on the first surface of the substrate, a thermal diffusion metal pattern on the first adhesive layer, multiple vias vertically extending from the thermal diffusion metal pattern into the substrate through the first adhesive layer with a gap around each of the vias in the substrate and the first adhesive layer, and a second adhesive layer on the second surface of the substrate. The thermal diffusion metal pattern is not to be electrically connected to a semiconductor device to be mounted. The second adhesive layer fills in the gap around each of the vias within the substrate and the first adhesive layer. The gap includes a first gap and a second gap in the substrate and the first adhesive layer, respectively. The second gap is greater in lateral size than the first gap.Type: ApplicationFiled: April 5, 2016Publication date: October 20, 2016Inventor: Kazutaka KOBAYASHI
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Publication number: 20160284585Abstract: A substrate holding method is to horizontally hold a substrate, and includes a positioning step of positioning a substrate by moving a substrate transfer mechanism and by allowing the peripheral edge of the substrate to come into contact with the plurality of positioning pins, a substrate grasping step of bringing the plurality of grasping pins into a closed state after completing the positioning step so that the substrate held by the plurality of positioning pins and the plurality of grasping pins, and a transfer mechanism receding step of allowing the substrate transfer mechanism to recede from above the spin base after completing the substrate grasping step.Type: ApplicationFiled: March 25, 2016Publication date: September 29, 2016Inventors: Kazutaka KOBAYASHI, Hiroshi KATO
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Publication number: 20160157345Abstract: A wiring substrate includes an electronic component mounting pad, an electrode pad arranged at an outer side of the electronic component mounting pad, a first insulation layer formed on the electronic component mounting pad and the electrode pad, an opening formed in the first insulation layer on the electronic component mounting pad, a connection hole formed in the first insulation layer on the electrode pad, and recess portions formed at the electronic component mounting pad in the opening and at the electrode pad in the connection hole, respectively.Type: ApplicationFiled: November 24, 2015Publication date: June 2, 2016Inventor: Kazutaka Kobayashi
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Patent number: 9282629Abstract: A wiring substrate includes a heat spreader, a first insulating layer provided on the heat spreader via an adhesion layer, the first insulating layer, a plurality of through wirings formed to fill through holes provided at the first insulating layer, respectively, a thermal diffusion wiring provided on the first insulating layer so as to be connected to the through wirings, the thermal diffusion wiring being configured not to be electrically connected to a semiconductor device, an electrical connection wiring provided on the first insulating layer, the electrical connection wiring being configured to be electrically connected to the semiconductor device, wherein the heat spreader is provided with a projection portion, made of a composition same as the heat spreader, at a surface of the heat spreader on which the adhesion layer is formed, the projection portion being aimed at least at an area overlapping the through wirings in a plan view.Type: GrantFiled: December 26, 2014Date of Patent: March 8, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Yasuyoshi Horikawa, Tatsuaki Denda, Hiroshi Shimizu, Kazutaka Kobayashi
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Patent number: 9192049Abstract: A wiring substrate for a semiconductor device includes a heat spreader; a polyimide layer provided with through holes and provided on the heat spreader via an adhesion layer; through wirings formed to fill the through holes of the polyimide layer; a thermal diffusion wiring provided on the polyimide layer and is configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring and is configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer with a first open portion and a second open portion that expose the electrical connection wiring and the thermal diffusion wiring, respectively, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring.Type: GrantFiled: November 10, 2014Date of Patent: November 17, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Tatsuaki Denda, Kazutaka Kobayashi
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Publication number: 20150319841Abstract: A wiring board includes a heat dissipation plate, a heat-conductive adhesive layer, an insulating layer, a thermal via, a heat dissipation metal terminal, and electrodes. The heat-conductive adhesive layer is disposed on the heat dissipation plate. The insulating layer is disposed on the heat-conductive adhesive layer. The insulating layer is formed with an opening portion. The thermal via is disposed in the opening portion of the insulating layer. The heat dissipation metal terminal is disposed on the thermal via and electrically connected to the heat dissipation plate. The electrodes are disposed on the insulating layer. The electrodes are to be connected to an electronic component.Type: ApplicationFiled: April 28, 2015Publication date: November 5, 2015Inventor: Kazutaka Kobayashi
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Patent number: 9137890Abstract: There is provided a wiring board. The wiring board includes: a first insulating layer; a plurality of wiring patterns on the first insulating layer so as to be spaced apart from each other; a plating layer on at least one of the wiring patterns; a second insulating layer containing silicone therein and having an opening, wherein an outermost surface of the plating layer is exposed from the opening and serves as a connection pad; and a silica film on the outermost surface of the plating layer.Type: GrantFiled: February 11, 2014Date of Patent: September 15, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kazutaka Kobayashi, Mitsuhiro Aizawa, Hiroshi Shimizu, Mina Iwai
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Publication number: 20150230328Abstract: A wiring substrate includes a heat spreader; a first insulating layer provided on the heat spreader via an adhesion layer, the first insulating layer; a plurality of through wirings formed to fill through holes provided at the first insulating layer, respectively; a thermal diffusion wiring provided on the first insulating layer so as to be connected to the through wirings, the thermal diffusion wiring being configured not to be electrically connected to a semiconductor device; an electrical connection wiring provided on the first insulating layer, the electrical connection wiring being configured to be electrically connected to the semiconductor device, wherein the heat spreader is provided with a projection portion, made of a composition same as the heat spreader, at a surface of the heat spreader on which the adhesion layer is formed, the projection portion being formed at least at an area overlapping the through wirings in a plan view.Type: ApplicationFiled: December 26, 2014Publication date: August 13, 2015Inventors: Yasuyoshi HORIKAWA, Tatsuaki DENDA, Hiroshi SHIMIZU, Kazutaka KOBAYASHI
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Publication number: 20150200337Abstract: A wiring substrate for a semiconductor device includes a heat spreader; a polyimide layer provided with through holes and provided on the heat spreader via an adhesion layer; through wirings formed to fill the through holes of the polyimide layer; a thermal diffusion wiring provided on the polyimide layer and is configured not to be electrically connected to the semiconductor device; an electrical connection wiring provided on the polyimide layer at a same plane with the thermal diffusion wiring and is configured to be electrically connected to the semiconductor device; and an insulating layer provided on the polyimide layer with a first open portion and a second open portion that expose the electrical connection wiring and the thermal diffusion wiring, respectively, the thermal diffusion wiring being formed to extend at an outer side of the second open portion and have a larger area than the electrical connection wiring.Type: ApplicationFiled: November 10, 2014Publication date: July 16, 2015Inventors: Tatsuaki DENDA, Kazutaka KOBAYASHI