Patents by Inventor Kazutaka Miyamoto

Kazutaka Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818355
    Abstract: Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: October 27, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Takaaki Fuchikami, Kazutaka Miyamoto, Hiromitsu Kimura, Kazuhisa Ukai
  • Publication number: 20190341109
    Abstract: Disclosed is a semiconductor memory device including a memory cell based on a static random access memory having a 6T or 4T2R configuration and including a first internal node, a second internal node, a first ferroelectric capacitor, and a second ferroelectric capacitor, the first ferroelectric capacitor and the second ferroelectric capacitor having respective first ends connected respectively to the first internal node and the second internal node. For recovering data stored in a non-volatile fashion in the first ferroelectric capacitor and the second ferroelectric capacitor, a first access transistor connected between the first internal node and a first bit line and a second access transistor connected between the second internal node and a second bit line are turned on, and respective capacitive components of the first bit line and the second bit line are used as load capacitances.
    Type: Application
    Filed: April 30, 2019
    Publication date: November 7, 2019
    Inventors: TAKAAKI FUCHIKAMI, KAZUTAKA MIYAMOTO, HIROMITSU KIMURA, KAZUHISA UKAI
  • Patent number: 10259099
    Abstract: The method forms a porous polyurethane polishing pad by coagulating thermoplastic polyurethane to create a porous matrix having large pores extending upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. Heating a press to temperature below or above the softening onset temperature of the thermoplastic polyurethane forms a series of pillows. Plastic deforming side walls of the pillow structures forms downwardly sloped side walls. The downwardly sloped side walls extend from all sides of the pillow structures. The large pores open to the downwardly sloped sidewalls are less vertical than the large pores open to the top polishing surface and are offset 10 to 60 degrees from the vertical direction.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: April 16, 2019
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
  • Patent number: 9925637
    Abstract: The porous polyurethane polishing pad includes a porous polyurethane matrix having large pores extending upward from a base surface and open to a polishing surface. A series of pillow structures is formed from the porous matrix that include the large pores and the small pores. The pillow structures have a downward surface extending from the top polishing surface for forming downwardly sloped side walls at an angle from 30 to 60 degrees from the polishing surface. The large pores open to the downwardly sloped sidewalls and are less vertical than the large pores. The large pores are offset 10 to 60 degrees from the vertical direction in a direction more orthogonal to the sloped sidewalls.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: March 27, 2018
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
  • Publication number: 20180036860
    Abstract: The method forms a porous polyurethane polishing pad by coagulating thermoplastic polyurethane to create a porous matrix having large pores extending upward from a base surface and open to an upper surface. The large pores are interconnected with small pores. Heating a press to temperature below or above the softening onset temperature of the thermoplastic polyurethane forms a series of pillows. Plastic deforming side walls of the pillow structures forms downwardly sloped side walls. The downwardly sloped side walls extend from all sides of the pillow structures. The large pores open to the downwardly sloped sidewalls are less vertical than the large pores open to the top polishing surface and are offset 10 to 60 degrees from the vertical direction.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
  • Publication number: 20180036862
    Abstract: The porous polyurethane polishing pad includes a porous polyurethane matrix having large pores extending upward from a base surface and open to a polishing surface. A series of pillow structures is formed from the porous matrix that include the large pores and the small pores. The pillow structures have a downward surface extending from the top polishing surface for forming downwardly sloped side walls at an angle from 30 to 60 degrees from the polishing surface. The large pores open to the downwardly sloped sidewalls and are less vertical than the large pores. The large pores are offset 10 to 60 degrees from the vertical direction in a direction more orthogonal to the sloped sidewalls.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 8, 2018
    Inventors: Koichi Yoshida, Kazutaka Miyamoto, Katsumasa Kawabata, Henry Sanford-Crane, Hui Bin Huang, George C. Jacob, Shuiyuan Luo
  • Patent number: 8980749
    Abstract: A method for polishing a silicon wafer is provided, comprising: providing a silicon wafer; providing a polishing pad having a polishing layer which is the reaction product of raw material ingredients, including: a polyfunctional isocyanate; and, a curative package; wherein the curative package contains an amine initiated polyol curative and a high molecular weight polyol curative; wherein the polishing layer exhibits a density of greater than 0.4 g/cm3; a Shore D hardness of 5 to 40; an elongation to break of 100 to 450%; and, a cut rate of 25 to 150 ?m/hr; and, wherein the polishing layer has a polishing surface adapted for polishing the silicon wafer; and, creating dynamic contact between the polishing surface and the silicon wafer.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: March 17, 2015
    Assignees: Rohm and Haas Electronic Materials CMP Holdings, Inc., Nitta Haas Incorporated
    Inventors: Yasuyuki Itai, Bainian Qian, Hiroyuki Nakano, David B. James, Naoko Kawai, Katsumasa Kawabata, Koichi Yoshida, Kazutaka Miyamoto, James Murnane, Fengji Yeh, Marty W. DeGroot
  • Patent number: 6807888
    Abstract: There is provided a recording material cutting device having a mechanism for cutting a recording material by the whole edge of a cutter blade so as to prolong the service life of the cutter blade, while allowing to simplify the structure of the device, to downsize the device, and to improve the straightness of the cut portion of the recording material. Upon starting the cutting, the cutting-in depth of the cutter blade 130 is the deepest, and the recording material 113 is cut by the near-root portion of the cutter blade 130. As the whole of the cutter unit 112 moves in the direction C while the seizing member 123 abuts onto the cammed surface of the cammed portion 132, the cutter holder 122 is gradually lifted up so that the cutting-in depth of the cutter blade 130 into the recording material 113 is gradually shallowed.
    Type: Grant
    Filed: November 9, 2001
    Date of Patent: October 26, 2004
    Assignee: Canon Finetech Inc.
    Inventors: Naoki Kiyohara, Yousuke Tatsumi, Kazutaka Miyamoto
  • Patent number: 6609791
    Abstract: Between adjacent pinch rollers 22, an auxiliary roller 44 is provided coaxially with the pinch rollers 22. A large diameter portion 44a of the auxiliary roller 44 presses down a recording medium on a platen 12. Between the auxiliary roller 44 and an image formation zone 41, there is provided a downstream sheet-pressing member 46. The large diameter portion 46a of the downstream sheet-pressing member 46 also presses down the recording medium against the platen 12.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: August 26, 2003
    Assignee: Canon Finetech Inc.
    Inventors: Kazutaka Miyamoto, Naruhiko Itou, Ryoma Suzuki
  • Publication number: 20020171706
    Abstract: Ink (pigment component ink) is jetted toward an ink absorber (34K) from the nozzle (22K) only of a print head (20K), with no ink jetted from print heads (20C, 20M, 20Y). Next, a carriage (24) is moved in an arrow B′ direction to position the print head (20C) directly above a cap (32K), at that time ink (dye component ink) is jetted toward the ink absorber (34K) from the nozzle (22C) only of the print head (20C) to allow the dye component ink to flow into a waste ink tube (36K). Then, ink (dye component ink) is similarly jetted toward the ink absorber (34K) from the nozzle (22M) only of the print head (20M), whereby the pigment component ink is allowed to flow smoothly without clogging a waste ink tube with a stuck, solid pigment component ink.
    Type: Application
    Filed: May 1, 2002
    Publication date: November 21, 2002
    Inventors: Kazutaka Miyamoto, Chihiro Maruyama