Patents by Inventor Kazutaka Terashima

Kazutaka Terashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9755111
    Abstract: A structure of a high luminance LED and a high luminance LD is provided. The present invention provides a light emitting device containing, on a zinc blend-type BP layer formed on an Si substrate, an AlyInxGazN (y?0, x>0) crystal as a mother crystal maintaining the zinc blend-type crystal structure and In dots having an In concentration higher than that of the AlyInxGazN (y?0, x>0) crystal as the mother crystal.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: September 5, 2017
    Assignees: NITTO OPTICAL CO., LTD., SOLARTES Lab, LTD.
    Inventors: Kazutaka Terashima, Suzuka Nishimura, Muneyuki Hirai
  • Patent number: 9595632
    Abstract: A method for producing a GaN-based crystal includes forming a Zinc-blend type BP crystal layer on a Si substrate; forming an In-containing layer, on the BP crystal layer, with such a thickness as to keep the Zinc-blend type structure; and forming a Zinc-blend type GaN-based crystal layer on the In-containing layer. The In-containing layer is a metallic In layer having a thickness of 4 atom layers or less, an InGaN layer having a thickness of 2 nm or less, an InAl mixture layer having a thickness of 4 atom layers or less and containing Al at 10% or less, or an AlInGaN layer having a thickness of 2 nm or less and containing Al at 10% or less.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: March 14, 2017
    Assignees: NITTO OPTICAL CO., LTD., SOLARTES Lab, Ltd.
    Inventors: Kazutaka Terashima, Suzuka Nishimura, Muneyuki Hirai
  • Publication number: 20160087153
    Abstract: A structure of a high luminance LED and a high luminance LD is provided. The present invention provides a light emitting device containing, on a zinc blende-type BP layer formed on an Si substrate, an AlyInxGazN (y?0, x>0) crystal as a mother crystal maintaining the zinc blende-type crystal structure and In dots having an In concentration higher than that of the AlyInxGazN (y?0, x>0) crystal as the mother crystal.
    Type: Application
    Filed: December 4, 2015
    Publication date: March 24, 2016
    Applicants: NITTO OPTICAL CO., LTD., SOLARTES Lab., LTD.
    Inventors: Kazutaka Terashima, Suzuka NISHIMURA, Muneyuki HIRAI
  • Publication number: 20150194569
    Abstract: A method for producing a GaN-based crystal includes forming a Zinc-blende type BP crystal layer on a Si substrate; forming an In-containing layer, on the BP crystal layer, with such a thickness as to keep the Zinc-blende type structure; and forming a Zinc-blende type GaN-based crystal layer on the In-containing layer. The In-containing layer is a metallic In layer having a thickness of 4 atom layers or less, an InGaN layer having a thickness of 2 nm or less, an InAl mixture layer having a thickness of 4 atom layers or less and containing Al at 10% or less, or an AlInGaN layer having a thickness of 2 nm or less and containing Al at 10% or less.
    Type: Application
    Filed: February 23, 2015
    Publication date: July 9, 2015
    Applicants: SOLARTES LAB., LTD., NITTO OPTICAL CO., LTD.
    Inventors: Kazutaka TERASHIMA, Suzuka NISHIMURA, Muneyuki HIRAI
  • Patent number: 7875118
    Abstract: A crystallization method includes the steps of melting a crystallized material in a crucible by heating, and growing a crystal by cooling and coagulating the melted material, wherein said melting step includes introducing a predetermined gas into the melted material.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: January 25, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasunao Oyama, Kazutaka Terashima
  • Publication number: 20100297786
    Abstract: The present invention provides a method for manufacturing a compound semiconductor, which can improve a quality of each of thin film layers constituting a laminate structure. Each of first and second thin film layers is formed by growing a crystal of each thin film layer one over another on a silicon substrate 2 in first and second vapor deposition chambers 6a and 6b for exclusive use, corresponding to the respective thin film layers. As this crystal growth is carried out under conditions under which nothing other than raw gas materials used therein or those derived therefrom, such as stuck materials, precipitates, etc., exists in the first and second vapor deposition chambers 6a and 6b, a decrease in quality of the second thin film layer can be prevented because an unexpected reaction between the raw gas materials used for the first and second thin film layers, etc. can be suppressed.
    Type: Application
    Filed: March 20, 2007
    Publication date: November 25, 2010
    Applicants: Nitto Koki Kabushiki Kaisha, Yugen Kaisha Solates Labo
    Inventors: Kazutaka Terashima, Suzuka Nishimura, Hirosi Nagayoshi, Hiroshi Kawamura, Kazuhiro Haga
  • Patent number: 7696690
    Abstract: A short-wavelength light-emitting element such as an ultraviolet light-emitting element or blue light-emitting element is arranged in a container which has a window with a window board formed of calcium fluoride crystals. Fluoride crystals are ones which contain either metal or metal halide, or both of them. In a production method of fluoride crystals in which the cavity of a crucible is filled with raw material powder and this crucible is heated in a vertical Bridgman furnace, a production method of fluoride crystals of the present invention is the one in which the shortest diameter of a cross section of the cavity of the crucible is small. In a crucible, whose cavity is filled with raw material powder, heated in a vertical Bridgman furnace to produce fluoride crystals, a crucible is the one in which the shortest diameter of a section of the cavity is small.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: April 13, 2010
    Assignee: Japan Science and Technolgoy Agency
    Inventors: Kazutaka Terashima, Suzuka Nishimura
  • Publication number: 20080134962
    Abstract: A crystallization method includes the steps of melting a crystallized material in a crucible by heating, and growing a crystal by cooling and coagulating the melted material, wherein said melting step includes introducing a predetermined gas into the melted material.
    Type: Application
    Filed: October 22, 2007
    Publication date: June 12, 2008
    Inventors: Yasunao OYAMA, Kazutaka Terashima
  • Publication number: 20060038194
    Abstract: In the present invention, a short-wavelength light-emitting element such as an ultraviolet light-emitting element or blue light-emitting element is arranged in a container which has a window with a window board formed of calcium fluoride crystals. According to the present invention, it is possible to obtain a reliable light-emitting element device. Fluoride crystals of the present invention are ones which contain either metal or metal halide, or both of them. In a production method of fluoride crystals in which the cavity of a crucible is filled with raw material powder and this crucible is heated in a vertical Bridgman furnace, a production method of fluoride crystals of the present invention is the one in which the shortest diameter of a cross section of the cavity of the crucible is small.
    Type: Application
    Filed: June 24, 2005
    Publication date: February 23, 2006
    Inventors: Kazutaka Terashima, Suzuka Nishimura
  • Patent number: 6936490
    Abstract: A method of epitaxially growing a SiC film on a Si substrate, including: (a) supplying a raw material gas containing a gas having P (phosphorus) element and a gas having B (boron) element on a Si substrate, and thereby synthesizing an amorphous BP thin film having a thickness of 5 nm or more and 100 nm or less on the Si substrate; (b) further supplying a raw material gas containing a gas having P element and a gas having B element on the Si substrate, and thereby synthesizing a cubic boron phosphide single crystal film having a thickness of 5 nm or more and 1000 nm or less on the Si substrate; and (c) supplying a gas having carbon element and a gas having silicon element on the Si substrate thereon the BP single crystal film is formed, and thereby synthesizing a beta-SiC single crystal film or an amorphous SiC film having a thickness of 1 nm or more and several hundreds nanometers or less on the cubic boron phosphide single crystal film on the Si substrate.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: August 30, 2005
    Assignee: Toshiba Ceramics Co, Ltd.
    Inventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Kazutaka Terashima, Jun Komiyama
  • Patent number: 6828169
    Abstract: A method of forming a group-III nitride semiconductor layer on a light-emitting device. First, a substrate is provided. Next, a buffer layer is formed on the substrate. A hydrogen treatment is performed on the buffer layer. Finally, a group-III nitride semiconductor layer is formed on the buffer layer. According to the present invention, a hydrogen treatment is performed on the buffer to prevent corrosion during subsequent process and remove particles from the buffer layer. Thus, the structure of the epitaxy layer following formed on the buffer layer is enhanced.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: December 7, 2004
    Assignee: Vetra Technology, Inc.
    Inventors: Kazutaka Terashima, Mu-Jen Lai, Chiung-Yu Chang
  • Publication number: 20040053438
    Abstract: A method of epitaxially growing a SiC film on a Si substrate, including:
    Type: Application
    Filed: June 3, 2003
    Publication date: March 18, 2004
    Inventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Kazutaka Terashima, Juno Komiyama
  • Publication number: 20030224548
    Abstract: A method of forming a group-III nitride semiconductor layer on a light-emitting device. First, a substrate is provided. Next, a buffer layer is formed on the substrate. A hydrogen treatment is performed on the buffer layer. Finally, a group-III nitride semiconductor layer is formed on the buffer layer. According to the present invention, a hydrogen treatment is performed on the buffer to prevent corrosion during subsequent process and remove particles from the buffer layer. Thus, the structure of the epitaxy layer following formed on the buffer layer is enhanced.
    Type: Application
    Filed: June 17, 2003
    Publication date: December 4, 2003
    Inventors: Kazutaka Terashima, Mu-Jen Lai, Chiung-Yu Chang
  • Publication number: 20030198301
    Abstract: A method of epitaxial lateral overgrowth. First, a silicon substrate is provided. Next, a selective growth mask is formed on the substrate. The selective growth mask is patterned to form a plurality of opening windows between the adjacent patterned selective growth masks so as to expose the surface of the substrate thereon. Finally, a BP epitaxial layer is formed by vertically overgrowing the BP epitaxial layer on the surface of the substrate in the opening windows until the BP epitaxial layer is thicker than the patterned selective growth mask, and laterally overgrowing the BP epitaxial layer on the patterned selective growth mask.
    Type: Application
    Filed: June 17, 2003
    Publication date: October 23, 2003
    Inventors: Kazutaka Terashima, Mu-Jen Lai, Chiung-Yu Chang
  • Patent number: 6194744
    Abstract: A method of growing a group III nitride semiconductor crystal layer includes a step of growing a first buffer layer composed of boron phosphide on a silicon single crystal substrate by a vapor phase growth method at a temperature of not lower than 200° C. and not higher than 700° C., a step of growing a second buffer layer composed of boron phosphide on the first buffer layer by a vapor phase growth method at a temperature of not lower than 750° C. and not higher than 1200° C., and a step of growing a crystal layer composed of group III nitride semiconductor crystal represented by general formula AlpGaqInrN (where 0≦p≦1, 0≦q≦1, 0≦r≦1, p+q+r=1) on the second buffer layer by a vapor phase growth method. A semiconductor device incorporating the group III nitride semiconductor crystal layer is provided.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: February 27, 2001
    Assignee: Showa Denko Kabushiki Kaisha
    Inventors: Takashi Udagawa, Kazutaka Terashima, Suzuka Nishimura, Takuji Tsuzaki
  • Patent number: 6096128
    Abstract: A germanium layer 19 is melted on top of a starting polycrystalline silicon ingot 18, at a temperature below the melting point of pure silicon. Silicon is dissolved at the interface and floats to the top of the germanium melt to form a silicon melt layer 11, from which a crystal 20 can be drawn. The process permits the production of large diameter crystal with low oxygen content and no more than one percent germanium.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: August 1, 2000
    Assignees: Toshiba Ceramics Co., Ltd., Komatsu Electronic Metals Co., Ltd., Japan Science and Technology Corporation, Mitsubishi Materials Silicon corporation
    Inventors: Hideo Nakanishi, Susumu Maeda, Keisei Abe, Kazutaka Terashima
  • Patent number: 6069021
    Abstract: A method of growing a group III nitride semiconductor crystal layer includes a step of growing a first buffer layer composed of boron phosphide on a silicon single crystal substrate by a vapor phase growth method at a temperature of not lower than 200.degree. C. and not higher than 700.degree. C., a step of growing a second buffer layer composed of boron phosphide on the first buffer layer by a vapor phase growth method at a temperature of not lower than 750.degree. C. and not higher than 1200.degree. C., and a step of growing a crystal layer composed of group III nitride semiconductor crystal represented by general formula Al.sub.p Ga.sub.q In.sub.r N (where 0.ltoreq.p.ltoreq.1, 0.ltoreq.q.ltoreq.1, 0.ltoreq.r.ltoreq.1, p+q+r=1) on the second buffer layer by a vapor phase growth method. A semiconductor device incorporating the group III nitride semiconductor crystal layer is provided.
    Type: Grant
    Filed: March 17, 1999
    Date of Patent: May 30, 2000
    Assignee: Showa Denko K.K.
    Inventors: Kazutaka Terashima, Suzuka Nishimura, Takuji Tsuzaki, Takashi Udagawa
  • Patent number: 6019837
    Abstract: A temperature sensor 42 is provided in a furnace 11, measuring temperature above a molten liquid 24 put in a crucible 12 to check proceedings of evaporation of oxygen vaporized from a free surface 44 of the molten liquid 24. From the data, and considering the relation with the oxygen dissolved into the crucible 12, the oxygen concentration in the molten liquid 24 can be found and the amount of oxygen taken into a single silicon crystal 40 pulled up from the molten liquid 24 can be figured out.
    Type: Grant
    Filed: November 25, 1997
    Date of Patent: February 1, 2000
    Assignees: Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Silicon Corporation, Kagaku Gijutsu Sinkou Jigyo Dan, Toshiba Ceramics Co., Ltd.
    Inventors: Susumu Maeda, Keisei Abe, Kazutaka Terashima, Hideo Nakanishi
  • Patent number: 6004393
    Abstract: A temperature sensor 42 is provided in a furnace 11, measuring temperature above a molten liquid 24 put in a crucible 12 to check proceedings of evaporation of oxygen vaporized from a free surface 44 of the molten liquid 24. From the data, and considering the relation with the oxygen dissolved into the crucible 12, the oxygen concentration in the molten liquid 24 can be found and the amount of oxygen taken into a single silicon crystal 40 pulled up from the molten liquid 24 can be figured out.
    Type: Grant
    Filed: January 22, 1999
    Date of Patent: December 21, 1999
    Assignees: Komatsu Electronic Metals Co., Ltd., Mitsubishi Materials Silicon Corporation, Kagaku Gijutsu Sinkou Jigyo Dan, Toshiba Ceramics Co., Ltd.
    Inventors: Susumu Maeda, Keisei Abe, Kazutaka Terashima, Hideo Nakanishi
  • Patent number: 5524574
    Abstract: The amount of Group-V element included in a melt 6 has the close relationship with the oxygen concentration of the melt 6. This relationship is utilized for controlling the oxygen concentration of a single crystal 8 at a high level. The content of Group-V element is calculated from the weight of the melt 6 gauged by a gravimeter 11 and compared with a preset value in a control unit 12. When the calculated content is smaller than the preset value, the control signal to additionally supply Group-V element to the melt 6 is outputted from the control unit 12 to a feeder 14. When the calculated content is larger than the preset value, the control signal to supply a raw material to the melt 6 is outputted to another feeder 13.
    Type: Grant
    Filed: August 17, 1994
    Date of Patent: June 11, 1996
    Assignees: Research Development Corporation of Japan, Kouji Izunome, Kazutaka Terashima, Yutaka Shiraishi, Hitoshi Sasaki
    Inventors: Xingming Huang, Kouji Izunome, Kazutaka Terashima, Yutaka Shiraishi, Hitoshi Sasaki, Shigeyuki Kimura