Patents by Inventor Kazutoshi Nakamura

Kazutoshi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418470
    Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: September 17, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Publication number: 20190238698
    Abstract: An image reading apparatus includes: a supply tray, which supports sheets to be supplied and includes a movable plate configured to move from a first position to a second position as the sheet supported by the paper feed tray is decreased, the second position being higher than the first position; a discharge tray; a conveyance guide; a reading sensor; a discharge unit, which includes a discharge opening to discharge the sheet conveyed by the conveyance guide to the discharge tray and is configured to move from a third position to a fourth position as the sheet supported by the paper feed tray is decreased, the fourth position being higher than the third position; and a first drive source, which generates a drive force, wherein the discharge unit is configured to move by receiving the drive force and to transmit the drive force to the movable plate.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 1, 2019
    Inventors: Takashi Fujiwara, Kazutoshi Nakamura
  • Publication number: 20190081162
    Abstract: A semiconductor device according to an embodiment includes a first diode portion including a first trench extending in a first direction, and a first trench electrode; a second diode portion adjacent to the first diode portion in the first direction and includes a second trench extending in the first direction, and a second trench electrode and of which the width in the first direction is greater than the width of the first diode portion in a second direction perpendicular to the first direction; and a first IGBT portion adjacent to the first diode portion in the second direction and is adjacent to the second diode portion in the first direction and includes a third trench extending in the first direction, and a first gate electrode.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 14, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Ryohei GEJO, Kazutoshi NAKAMURA, Norio YASUHARA, Tomohiro TAMAKI
  • Patent number: 10083957
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 25, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
  • Publication number: 20180226399
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed.
    Type: Application
    Filed: September 8, 2017
    Publication date: August 9, 2018
    Inventors: Tomohiro Tamaki, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 9876011
    Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a higher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Matsushita, Kazutoshi Nakamura
  • Patent number: 9787242
    Abstract: Temperature-dependent motor control device, including: a motor controller configured to switch a motor control state among an activated state in which the motor is activated by a first current, an activation stopped state in which activation of the motor is stopped by stopping current supply, and an activation suspended state in which activation of the motor is suspended with a second current smaller than the first current kept supplied; and a temperature estimator configured to calculate an estimated motor temperature value and to perform a first calculation for gradually increasing the estimated value when the motor is in the activated state, a second calculation for gradually decreasing the estimated value when the motor is in the activation stopped state, and a third calculation for gradually decreasing the estimated value at a rate of decrease lower than that in the second calculation when the motor is in the activation suspended state.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: October 10, 2017
    Assignee: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Kazutoshi Nakamura, Masanori Hamaguchi
  • Patent number: 9761582
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: September 12, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Patent number: 9692921
    Abstract: An image reading device includes a housing, a first support member, a reading unit, a movable member, and a flat cable. The housing defines an accommodating space between a bottom surface and a frame member facing the bottom surface. The first support member is supported by the housing and covers the accommodating space. The movable member holds the reading unit disposed in the accommodating space. The flat cable is connected to the reading unit at one end and an electrical part outside the accommodating space at the other end. The housing further includes a support wall protruding from the bottom surface toward the first support member and a cable receiving portion receiving a middle portion of the flat cable. The cable receiving portion is formed at a higher height level than a particular area of the bottom surface located between the support wall and the cable receiving portion.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: June 27, 2017
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventor: Kazutoshi Nakamura
  • Publication number: 20170148786
    Abstract: A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; an insulating portion provided on the first semiconductor region; a third semiconductor region of the second conductivity type provided on the second semiconductor region and having a hicher carrier concentration of the second conductivity type than that of the second semiconductor region; and a first electrode provided on the insulating portion and the third semiconductor region, the first electrode having a portion which is aligned with the second semiconductor region in a second direction perpendicular to a first direction being from the first semiconductor region to the second semiconductor region, and the first electrode being in contact with the second semiconductor region and the third semiconductor region.
    Type: Application
    Filed: September 6, 2016
    Publication date: May 25, 2017
    Inventors: Kenichi Matsushita, Kazutoshi Nakamura
  • Publication number: 20170110449
    Abstract: A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type; a third semiconductor region of the second conductivity type provided between the first semiconductor region and the second semiconductor region on the first electrode and having a higher carrier concentration of the second conductivity type than the second semiconductor region; a fourth semiconductor region; a fifth semiconductor region; a sixth semiconductor region; a seventh semiconductor region; a gate electrode; a gate insulating layer; and a second electrode provided on the fifth semiconductor region and the seventh semiconductor region.
    Type: Application
    Filed: September 2, 2016
    Publication date: April 20, 2017
    Inventors: Ryohei Gejo, Kazutoshi Nakamura, Norio Yasuhara, Tomohiro Tamaki
  • Patent number: 9620631
    Abstract: A power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a pair of conductive bodies, a third semiconductor layer of the second conductivity type, and a fourth semiconductor layer of the first conductivity type. The second semiconductor layer is provided on the first semiconductor layer on the first surface side. The pair of conductive bodies are provided via an insulating film in a pair of first trenches extending across the second semiconductor layer from a surface of the second semiconductor layer to the first semiconductor layer. The third semiconductor layer is selectively formed on the surface of the second semiconductor layer between the pair of conductive bodies and has a higher second conductivity type impurity concentration in a surface of the third semiconductor layer than the second semiconductor layer.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: April 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Yuichi Oshino, Hideaki Ninomiya, Kazutoshi Nakamura
  • Publication number: 20160227059
    Abstract: An image reading device includes a housing, a first support member, a reading unit, a movable member, and a flat cable. The housing defines an accommodating space between a bottom surface and a frame member facing the bottom surface. The first support member is supported by the housing and covers the accommodating space. The movable member holds the reading unit disposed in the accommodating space. The flat cable is connected to the reading unit at one end and an electrical part outside the accommodating space at the other end. The housing further includes a support wall protruding from the bottom surface toward the first support member and a cable receiving portion receiving a middle portion of the flat cable. The cable receiving portion is formed at a higher height level than a particular area of the bottom surface located between the support wall and the cable receiving portion.
    Type: Application
    Filed: January 29, 2016
    Publication date: August 4, 2016
    Inventor: Kazutoshi Nakamura
  • Publication number: 20160156300
    Abstract: Temperature-dependent motor control device, including: a motor controller configured to switch a motor control state among an activated state in which the motor is activated by a first current, an activation stopped state in which activation of the motor is stopped by stopping current supply, and an activation suspended state in which activation of the motor is suspended with a second current smaller than the first current kept supplied; and a temperature estimator configured to calculate an estimated motor temperature value and to perform a first calculation for gradually increasing the estimated value when the motor is in the activated state, a second calculation for gradually decreasing the estimated value when the motor is in the activation stopped state, and a third calculation for gradually decreasing the estimated value at a rate of decrease lower than that in the second calculation when the motor is in the activation suspended state.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Applicant: BROTHER KOGYO KABUSHIKI KAISHA
    Inventors: Kazutoshi NAKAMURA, Masanori HAMAGUCHI
  • Patent number: 9337189
    Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.
    Type: Grant
    Filed: May 11, 2015
    Date of Patent: May 10, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
  • Patent number: 9324815
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 9318588
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: April 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
  • Patent number: 9312337
    Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: April 12, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Kazutoshi Nakamura
  • Patent number: 9257507
    Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: February 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichiro Misu, Kazutoshi Nakamura
  • Patent number: 9214535
    Abstract: A collector layer of a first conductivity type is provided in the IGBT region and the boundary region and functions as a collector of the IGBT in the IGBT region. A cathode layer of a second conductivity type is provided in the diode region apart from the collector layer and functions as a cathode of the diode. A drift layer of the second conductivity type is provided in the IGBT region, the boundary region, and the diode region, the drift layer being provided on sides of the collector layer and the cathode layer opposite the first electrode. A diffusion layer of the first conductivity type is provided in the boundary region on a side of the drift layer opposite the first electrode.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: December 15, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Yuichi Oshino, Hideaki Ninomiya, Yoshiko Ikeda