Patents by Inventor Kazutoshi Nakamura
Kazutoshi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150340478Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.Type: ApplicationFiled: August 5, 2015Publication date: November 26, 2015Inventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
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Publication number: 20150263150Abstract: According to one embodiment, a semiconductor device including: a first electrode; a second electrode having a portion extending toward the first electrode side; a first semiconductor layer; a first semiconductor region provided between the first semiconductor layer and the second electrode; a second semiconductor region provided between the first semiconductor region and the second electrode, and the second semiconductor region being in contact with the portion; a third electrode provided between the first electrode and the portion, and the third electrode being connected to the portion; a fourth electrode provided on the first semiconductor layer, the first semiconductor region, and the second semiconductor region via a second insulating film; and a third semiconductor region provided between the first semiconductor region and the second semiconductor region, and the third semiconductor region having a higher impurity concentration than the first semiconductor region.Type: ApplicationFiled: September 10, 2014Publication date: September 17, 2015Inventors: Tomoko Matsudai, Tsuneo Ogura, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 9130007Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.Type: GrantFiled: March 7, 2014Date of Patent: September 8, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
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Publication number: 20150243656Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: ApplicationFiled: May 11, 2015Publication date: August 27, 2015Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Publication number: 20150236104Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: ApplicationFiled: May 1, 2015Publication date: August 20, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO
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Publication number: 20150228726Abstract: According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film.Type: ApplicationFiled: April 23, 2015Publication date: August 13, 2015Inventors: Tsuneo Ogura, Kazutoshi Nakamura
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Patent number: 9059236Abstract: According to one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode; a second semiconductor layer provided between the first semiconductor layer and the second electrode, and the second semiconductor layer having a lower impurity concentration than the first semiconductor layer; a first semiconductor region provided between part of the second semiconductor layer and the second electrode; a second semiconductor region provided between a portion different from the part of the second semiconductor layer and the second electrode, and the second semiconductor region being in contact with the first semiconductor region; and a third semiconductor region provided between at least part of the first semiconductor region and the second electrode.Type: GrantFiled: August 29, 2013Date of Patent: June 16, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Tomoko Matsudai, Yuichi Oshino, Shinichiro Misu, Yoshiko Ikeda, Kazutoshi Nakamura
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Patent number: 9054066Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.Type: GrantFiled: August 29, 2013Date of Patent: June 9, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
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Patent number: 9054152Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a control electrode disposed within and insulated from the first, second, and third semiconductor regions, a first electrode electrically connected with the second and third semiconductor regions, a second electrode, and a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region. The fourth semiconductor region includes a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, and a contact area of the first portion with the second electrode is larger than a contact area of the second area with the second electrode.Type: GrantFiled: February 28, 2014Date of Patent: June 9, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura
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Publication number: 20150091055Abstract: A semiconductor device includes a first region of a first conductivity type, a collector electrode electrically connected to a first side of the first region, first and second gate electrodes and first and second conductor electrodes, each of the gate and conductor electrodes extending into the first region from a second side thereof that is opposite to the first side, an emitter electrode electrically connected to the conductor electrodes, and a second region of the first conductivity type, that is adjacent to the gate electrodes, electrically connected to the emitter electrode, and spaced from the first and second conductor electrodes.Type: ApplicationFiled: February 28, 2014Publication date: April 2, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryohei GEJO, Kazutoshi NAKAMURA, Tsuneo OGURA, Tomoko MATSUDAI
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Patent number: 8981826Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: May 7, 2014Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20150069460Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type having first and second faces, and a second semiconductor layer of a second conductivity type disposed above the first face of the first semiconductor layer. The device further includes control electrodes facing the first and second semiconductor layers via insulating layers, and extending to a first direction parallel to the first face of the first semiconductor layer, and third semiconductor layers of the first conductivity type and fourth semiconductor layers of the second conductivity type alternately disposed along the first direction above the second semiconductor layer. The device further includes fifth semiconductor layers of the first conductivity type disposed below the second semiconductor layer or disposed at positions surrounded by the second semiconductor layer, the fifth semiconductor layers being arranged separately from one another along the first direction.Type: ApplicationFiled: March 7, 2014Publication date: March 12, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takuma Hara, Kazutoshi Nakamura, Tsuneo Ogura
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Publication number: 20150069461Abstract: This device includes a first base layer of a first conduction type. A second base-layer of a second conduction type is provided above the first base-layer. A first semiconductor layer of the first conduction type is above an opposite side of the second base-layer to the first base-layer. A second semiconductor layer of the second conduction type is above an opposite side of the first base-layer to the second base-layer. A plurality of first electrodes are provided at the first semiconductor layer and the second base-layer via first insulating films. A second electrode is provided between adjacent ones of the first electrodes and provided at the first semiconductor layer and the second base-layer via a second insulating film. A resistance of the first base-layer above a side of the second electrode is lower than a resistance of the first base-layer above a side of the first electrodes.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Shinichiro MISU, Kazutoshi NAKAMURA
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Publication number: 20150021655Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type on the first semiconductor region, a third semiconductor region of the first conductivity type on the second semiconductor region, a control electrode disposed within and insulated from the first, second, and third semiconductor regions, a first electrode electrically connected with the second and third semiconductor regions, a second electrode, and a fourth semiconductor region of the second conductivity type between the second electrode and the first semiconductor region. The fourth semiconductor region includes a first portion having a first dopant concentration and a second portion having a second dopant concentration higher than the first dopant concentration, and a contact area of the first portion with the second electrode is larger than a contact area of the second area with the second electrode.Type: ApplicationFiled: February 28, 2014Publication date: January 22, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tsuneo OGURA, Kazutoshi NAKAMURA
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Publication number: 20150021657Abstract: According to one embodiment, a semiconductor device includes: first and second electrodes; a first semiconductor region being in ohmic contact with the first electrode; a second semiconductor region being in contact with the first semiconductor region and the first electrode, and the second semiconductor region having a lower impurity concentration than the first semiconductor region; a first semiconductor layer; a second semiconductor layer; a third semiconductor region; a fourth semiconductor region being in contact with the second electrode; and a third electrode in contact with the second semiconductor layer, the third semiconductor region, and the fourth semiconductor region via an insulating film.Type: ApplicationFiled: March 10, 2014Publication date: January 22, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura
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Patent number: 8853775Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having first and second main surfaces, control electrodes disposed in trenches on the first main surface of the semiconductor substrate and extending in a first direction parallel to the first main surface, and control interconnects disposed on the first main surface of the semiconductor substrate and extending in a second direction perpendicular to the first direction. The semiconductor substrate includes a first semiconductor layer of a first conductivity type, second semiconductor layers of a second conductivity type on a surface of the first semiconductor layer on a first main surface side, third semiconductor layers of the first conductivity type disposed on surfaces of the second semiconductor layers on the first main surface side and extending in the second direction, and a fourth semiconductor layer of the second conductivity type on the second main surface of the semiconductor substrate.Type: GrantFiled: September 9, 2013Date of Patent: October 7, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tsuneo Ogura, Kazutoshi Nakamura, Hideaki Ninomiya, Tomoko Matsudai, Yuichi Oshino
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Publication number: 20140240015Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8760206Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: June 11, 2013Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 8734038Abstract: An image forming apparatus is provided that includes an image forming unit disposed in a main body and configured to form an image on a recording medium, an output tray provided in the main body and configured to receive the recording medium having an image formed thereon, and an ejection device provided in the main body and configured to eject the recording medium to the output tray. The apparatus may further include a movable sheet guiding member movably attached to the main body and a stationary sheet guiding member disposed downstream of the movable sheet guiding member in a recording medium ejection direction and above the output tray. The movable sheet guiding member can press a recording medium ejected from the ejection device downward, and the stationary sheet guiding member can protrude from the main body.Type: GrantFiled: September 24, 2011Date of Patent: May 27, 2014Assignee: Brother Kogyo Kabushiki KaishaInventors: Kazutoshi Nakamura, Takashi Saito
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Patent number: 8730542Abstract: A sheet feeding device including a roller to apply conveying force to one of a plurality of stacked sheets, a separator piece to apply conveying resistance to the stacked sheets and to nip the one of the stacked sheets in cooperation with the roller, a movable member being movable with respect to the roller, a pair of spring arms configured to contact the stacked sheets at an upstream position along a conveying direction with respect to a nipping position between the roller and the separator piece, and a bridge to bridge between the pair of spring arms, is provided. The bridge and the movable member are slidably in contact with each other at least when the sheet feeding device is in a conveyable condition.Type: GrantFiled: January 18, 2013Date of Patent: May 20, 2014Assignee: Brother Kogyo Kabushiki KaishaInventor: Kazutoshi Nakamura