Patents by Inventor Kazuya Kitsunai
Kazuya Kitsunai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11893237Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: February 3, 2022Date of Patent: February 6, 2024Assignee: Kioxia CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 11886335Abstract: According to one embodiment, a controller manages a first block set being a set of blocks in which a remaining time is a first time and a second block set being a set of blocks in which a remaining time is a second time. The controller calculates a first rewrite speed based on the first time and a number of blocks included in the first block set. The controller calculates a second rewriting speed based on the second time and a sum of the number of blocks included in the first block set and the number of blocks included in the second block set. The controller determines a maximum rewriting speed among the first rewrite speed and the second rewriting speed. The controller performs the rewrite operation at the determined maximum rewrite speed.Type: GrantFiled: June 13, 2022Date of Patent: January 30, 2024Assignee: Kioxia CorporationInventor: Kazuya Kitsunai
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Publication number: 20230185469Abstract: According to one embodiment, a controller manages a first block set being a set of blocks in which a remaining time is a first time and a second block set being a set of blocks in which a remaining time is a second time. The controller calculates a first rewrite speed based on the first time and a number of blocks included in the first block set. The controller calculates a second rewriting speed based on the second time and a sum of the number of blocks included in the first block set and the number of blocks included in the second block set. The controller determines a maximum rewriting speed among the first rewrite speed and the second rewriting speed. The controller performs the rewrite operation at the determined maximum rewrite speed.Type: ApplicationFiled: June 13, 2022Publication date: June 15, 2023Inventor: Kazuya KITSUNAI
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Patent number: 11645001Abstract: According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.Type: GrantFiled: January 13, 2021Date of Patent: May 9, 2023Assignee: Kioxia CorporationInventors: Chihoko Shigeta, Kazuya Kitsunai
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Publication number: 20230042619Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: October 27, 2022Publication date: February 9, 2023Applicant: Kioxia CorporationInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Patent number: 11513682Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: October 29, 2020Date of Patent: November 29, 2022Assignee: Kioxia CorporationInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20220155960Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: February 3, 2022Publication date: May 19, 2022Applicant: Kioxia CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 11287975Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: December 30, 2019Date of Patent: March 29, 2022Assignee: KIOXIA CORPORATIONInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20220066684Abstract: According to one embodiment, a memory system includes a first and second nonvolatile memory each including a plurality of memory cells; and a memory controller configured to perform, in parallel, a first set of write processes sequentially performed on the first nonvolatile memory, and a second set of write processes sequentially performed on the second nonvolatile memory. The memory controller is configured to change a setting of at least one unperformed write process among the first set and second set of write processes based on differences in progress between the first set and second set of write processes, the first set and second set of write processes being performed in parallel.Type: ApplicationFiled: January 13, 2021Publication date: March 3, 2022Applicant: Kioxia CorporationInventors: Chihoko SHIGETA, Kazuya KITSUNAI
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Patent number: 11182287Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.Type: GrantFiled: February 11, 2020Date of Patent: November 23, 2021Assignee: Kioxia CorporationInventors: Yoko Masuo, Yosuke Mitsumasu, Kazuya Kitsunai
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Publication number: 20210073118Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes a plurality of blocks. The controller controls an operation of writing data to the nonvolatile memory and an operation of reading data to the nonvolatile memory. The controller includes a first processor and a second processor. The first processor executes a first process of creating one or more free blocks by transferring valid data in N blocks (where N is a natural number greater than or equal to two) to blocks of number less than N. The second processor executes a second process of transferring valid data including data which needs refresh in M blocks (where M is a natural number greater than or equal to one) to blocks of number less than or equal to M.Type: ApplicationFiled: February 11, 2020Publication date: March 11, 2021Applicant: Kioxia CorporationInventors: Yoko MASUO, Yosuke MITSUMASU, Kazuya KITSUNAI
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Publication number: 20210042034Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: October 29, 2020Publication date: February 11, 2021Applicant: Toshiba Memory CorporationInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Patent number: 10845992Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: March 26, 2019Date of Patent: November 24, 2020Assignee: Toshiba Memory CorporationInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 10783034Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.Type: GrantFiled: September 7, 2018Date of Patent: September 22, 2020Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Chihoko Shigeta, Kazuya Kitsunai
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Patent number: 10649891Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.Type: GrantFiled: August 24, 2017Date of Patent: May 12, 2020Assignee: Toshiba Memory CorporationInventors: Satoshi Arai, Shunitsu Kohara, Kazuya Kitsunai, Yoshihisa Kojima, Hiroyuki Nemoto
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Publication number: 20200133496Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: December 30, 2019Publication date: April 30, 2020Applicant: Toshiba Memory CorporationInventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
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Patent number: 10558360Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: February 13, 2018Date of Patent: February 11, 2020Assignee: Toshiba Memory CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 10402097Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.Type: GrantFiled: September 6, 2018Date of Patent: September 3, 2019Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10372543Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.Type: GrantFiled: September 12, 2016Date of Patent: August 6, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuya Kitsunai, Shunitsu Kohara, Satoshi Arai, Yoshihisa Kojima
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Publication number: 20190220197Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Applicant: Toshiba Memory CorporationInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO