Patents by Inventor Kazuya Kitsunai

Kazuya Kitsunai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10783034
    Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: September 22, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Chihoko Shigeta, Kazuya Kitsunai
  • Patent number: 10649891
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Satoshi Arai, Shunitsu Kohara, Kazuya Kitsunai, Yoshihisa Kojima, Hiroyuki Nemoto
  • Publication number: 20200133496
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Patent number: 10558360
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 10402097
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10372543
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: August 6, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shunitsu Kohara, Satoshi Arai, Yoshihisa Kojima
  • Publication number: 20190220197
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Publication number: 20190196905
    Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.
    Type: Application
    Filed: September 7, 2018
    Publication date: June 27, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hiroyuki NEMOTO, Chihoko Shigeta, Kazuya Kitsunai
  • Patent number: 10248317
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Publication number: 20190018596
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.
    Type: Application
    Filed: September 6, 2018
    Publication date: January 17, 2019
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10095413
    Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: October 9, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai, Yoshihisa Kojima
  • Patent number: 10095410
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Patent number: 10019326
    Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory, a second memory, and a controller. The first memory stores translation information associating a logical address and a physical address. The second memory stores location information associating the logical address and a location of the translation information. The controller updates the translation information and the location information. After returning from a power supply interruption, the controller starts, at different timing, recovery of first location information and recovery of second location information. The first location information is a part of the location information. The second location information is a part of the location information different from the first location information. The controller executes processing different from recovery of the location information between the recovery of the first location information and the recovery of the second location information.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: July 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Akira Shimizu, Yoshihisa Kojima
  • Publication number: 20180165011
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 14, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Patent number: 9940071
    Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai
  • Patent number: 9933941
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Publication number: 20180088828
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Application
    Filed: November 21, 2017
    Publication date: March 29, 2018
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Publication number: 20180060228
    Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.
    Type: Application
    Filed: August 24, 2017
    Publication date: March 1, 2018
    Inventors: Satoshi ARAI, Shunitsu KOHARA, Kazuya KITSUNAI, Yoshihisa KOJIMA, Hiroyuki NEMOTO
  • Patent number: 9857984
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: January 2, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
  • Publication number: 20170269843
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: HIROKUNI YANO, SHINICHI KANNO, TOSHIKATSU HIDA, HIDENORI MATSUZAKI, KAZUYA KITSUNAI, SHIGEHIRO ASANO