Patents by Inventor Kazuya Kitsunai
Kazuya Kitsunai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10372543Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.Type: GrantFiled: September 12, 2016Date of Patent: August 6, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuya Kitsunai, Shunitsu Kohara, Satoshi Arai, Yoshihisa Kojima
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Publication number: 20190220197Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: March 26, 2019Publication date: July 18, 2019Applicant: Toshiba Memory CorporationInventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Publication number: 20190196905Abstract: According to one embodiment, in a memory system, a controller is configured to write a first data among write data to be written across the multiple chips of the first memory area into part of the first memory area and write, in response to a power supply disconnection being detected before writing a second data among the write data into the first memory area, a first information about a storage location where the second data has been stored and the second data into the second memory area. The controller is configured to read, in response to power return being detected, the first data from the part of the first memory area, and read the first information from the second memory area. The controller is configured to generate a second information about a reference location to access the second data based on the read first information.Type: ApplicationFiled: September 7, 2018Publication date: June 27, 2019Applicant: Toshiba Memory CorporationInventors: Hiroyuki NEMOTO, Chihoko Shigeta, Kazuya Kitsunai
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Patent number: 10248317Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: June 8, 2017Date of Patent: April 2, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20190018596Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.Type: ApplicationFiled: September 6, 2018Publication date: January 17, 2019Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10095413Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.Type: GrantFiled: July 13, 2016Date of Patent: October 9, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai, Yoshihisa Kojima
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Patent number: 10095410Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.Type: GrantFiled: November 21, 2017Date of Patent: October 9, 2018Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Patent number: 10019326Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a first memory, a second memory, and a controller. The first memory stores translation information associating a logical address and a physical address. The second memory stores location information associating the logical address and a location of the translation information. The controller updates the translation information and the location information. After returning from a power supply interruption, the controller starts, at different timing, recovery of first location information and recovery of second location information. The first location information is a part of the location information. The second location information is a part of the location information different from the first location information. The controller executes processing different from recovery of the location information between the recovery of the first location information and the recovery of the second location information.Type: GrantFiled: March 14, 2016Date of Patent: July 10, 2018Assignee: Toshiba Memory CorporationInventors: Kazuya Kitsunai, Akira Shimizu, Yoshihisa Kojima
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Publication number: 20180165011Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: February 13, 2018Publication date: June 14, 2018Applicant: Toshiba Memory CorporationInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 9940071Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.Type: GrantFiled: August 22, 2016Date of Patent: April 10, 2018Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Shunitsu Kohara, Kazuya Kitsunai, Satoshi Arai
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Patent number: 9933941Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: September 20, 2016Date of Patent: April 3, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20180088828Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.Type: ApplicationFiled: November 21, 2017Publication date: March 29, 2018Inventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Publication number: 20180060228Abstract: A storage device includes a nonvolatile memory, and a controller configured to perform, in response to commands from the host device, a read operation and a write operation on the nonvolatile memory. The controller divides a logical address space of the storage device into a plurality of subspaces and manages a priority value for each of the subspaces, the priority values of the subspaces determining an order for setting up the subspaces upon start-up of the storage device.Type: ApplicationFiled: August 24, 2017Publication date: March 1, 2018Inventors: Satoshi ARAI, Shunitsu KOHARA, Kazuya KITSUNAI, Yoshihisa KOJIMA, Hiroyuki NEMOTO
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Patent number: 9857984Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from a host, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the host before the first request is issued.Type: GrantFiled: December 24, 2015Date of Patent: January 2, 2018Assignee: Toshiba Memory CorporationInventors: Hiroyuki Nemoto, Kazuya Kitsunai, Yoshihisa Kojima, Katsuhiko Ueki
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Publication number: 20170269843Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: June 8, 2017Publication date: September 21, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: HIROKUNI YANO, SHINICHI KANNO, TOSHIKATSU HIDA, HIDENORI MATSUZAKI, KAZUYA KITSUNAI, SHIGEHIRO ASANO
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Publication number: 20170255564Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, a volatile second memory and a controller. The nonvolatile first memory stores translation information. The translation information associates a logical address and a physical address. The volatile second memory stores location information. The location information associates a logical address and a location where the translation information is stored in the first memory. The controller saves a first memory image in the first memory at a first timing, and saves a second memory image in the first memory at a second timing different from the first timing. The first memory image is a part of a memory image of the location information. The second memory image is another part, different form the first memory image, of the memory image of the location information.Type: ApplicationFiled: September 12, 2016Publication date: September 7, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Kazuya KITSUNAI, Shunitsu KOHARA, Satoshi ARAI, Yoshihisa KOJIMA
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Publication number: 20170220253Abstract: According to one embodiment, a memory system which is connectable to a host, the memory system includes a first memory as a nonvolatile memory storing information associated with an address translation between a logical address and a physical address, a second memory temporarily storing a part of the information at least, a first controller executing a read operation and a write operation of the information for the second memory in a first data unit, the first data unit being changeable and being a data size of one of regions obtained by dividing in a first address space, the part of the information at least stored in the first memory, and a second controller executing a read operation and a write operation of the information for the first memory in a second data unit different from the first data unit.Type: ApplicationFiled: July 13, 2016Publication date: August 3, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
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Publication number: 20170199687Abstract: According to one embodiment, a memory system includes a nonvolatile first memory, a second memory, and a processor. The second memory includes a first cache area for caching in units of a data-unit. The processor transfers the first data and translation information for the first data into the first memory and performs garbage collection. The garbage collection includes first to third process. The first process is determining whether second data is valid or invalid on the basis of translation information for the second data. The second data is corresponding to the first data in the first memory. The second process is copying third data within the first memory. The third data is corresponding to the second data determined to be valid. The third process is updating translation information for the third data. The processor caches, in the first cache area, only a data-unit including translation information for the first process.Type: ApplicationFiled: September 2, 2016Publication date: July 13, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI, Yoshihisa KOJIMA
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Patent number: 9703486Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: August 10, 2015Date of Patent: July 11, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20170160988Abstract: A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.Type: ApplicationFiled: August 22, 2016Publication date: June 8, 2017Inventors: Hiroyuki NEMOTO, Shunitsu KOHARA, Kazuya KITSUNAI, Satoshi ARAI