Patents by Inventor Kazuya Kitsunai
Kazuya Kitsunai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8583972Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.Type: GrantFiled: June 1, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20120311245Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: August 9, 2012Publication date: December 6, 2012Inventors: Hirokuni YANO, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20120239992Abstract: A method of controlling a nonvolatile semiconductor memory including a plurality of blocks, each one of the plurality of blocks being a unit of data erasing, includes determining a monitored block as a candidate for refresh operation from among the plurality of blocks based on a predetermined condition. The method includes monitoring an error count of data stored in the monitored block and not monitoring an error count of data stored in blocks excluding the monitored block among the plurality of blocks. The method also includes performing the refresh operation on data stored in the monitored block in which the error count is larger than a first threshold value.Type: ApplicationFiled: June 1, 2012Publication date: September 20, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu HIDA, Shinichi KANNO, Hirokuni YANO, Kazuya KITSUNAI, Shigehiro ASANO, Junji YANO
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Patent number: 8219861Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.Type: GrantFiled: October 11, 2011Date of Patent: July 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20120033496Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: ApplicationFiled: October 12, 2011Publication date: February 9, 2012Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
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Publication number: 20120030528Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.Type: ApplicationFiled: October 11, 2011Publication date: February 2, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu HIDA, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 8065471Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area.Type: GrantFiled: September 2, 2009Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 8065470Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: September 2, 2009Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 8060797Abstract: A semiconductor storage device can efficiently perform a refresh operation. A semiconductor storage device is provided which includes a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing. A controlling unit is further included monitoring an error count of data stored in a monitored block selected from the blocks and for refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.Type: GrantFiled: September 22, 2008Date of Patent: November 15, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Patent number: 8037277Abstract: A computer-readable storage medium stores a program for causing a processor to perform a process including: acquiring a first address that specifies a start address of a first area on the main memory where a target data to be cached is stored and range information that specifies a size of the first area on the main memory; converting the first address into a second address that specifies a start address of a second area on the local memory, the second area having a one-to-n correspondence (n=positive integer) to a part of a bit string of the first address; copying the target data stored in the first area specified by the first address and the range information onto the second area specified by the second address and the range information; and storing the second address to allow accessing the target data copied onto the local memory.Type: GrantFiled: February 28, 2008Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota, Kazuya Kitsunai
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Publication number: 20110219177Abstract: A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Kazuya Kitsunai, Junji Yano
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Patent number: 8015347Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: GrantFiled: September 2, 2009Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Patent number: 7962688Abstract: A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the fifth memory area, a fourth processing for moving an area of the third unit to the second memory area, a fifth processing for selecting and copying data to an empty area of the third unit in the second memory area, a sixth processing for moving an area of the third unit to the third memory area, and a seventh processing for selecting and copying data to an empty area of the third unit in the third memory area.Type: GrantFiled: September 2, 2009Date of Patent: June 14, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 7958411Abstract: A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.Type: GrantFiled: August 31, 2009Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Kazuya Kitsunai, Junji Yano
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Patent number: 7957933Abstract: An information processing apparatus includes a receptor for receiving an event signal occurring in hardware during program execution in time series, a feature event counter for counting the number of occurrences of a feature event to determine the feature of the program, a stored event counter for counting the number of occurrences of stored event determined from the feature event with the maximum number of occurrences, and a storage for storing the count result of the number of occurrences of the stored event.Type: GrantFiled: August 23, 2007Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Kitsunai, Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota
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Patent number: 7953920Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area.Type: GrantFiled: September 2, 2009Date of Patent: May 31, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 7949910Abstract: A memory system includes a nonvolatile memory including blocks as data erase units, a measuring unit which measures an erase time at which data in each block is erased, a block controller having a block table which associates a state value indicating one of a free state and a used state with the erase time for each block, a detector which detects blocks in which rewrite has collectively occurred within a short period, a first selector which selects a free block having an old erase time as a first block, a second selector which selects a block in use having an old erase time as a second block, and a leveling unit which moves data in the second block to the first block if the first block is included in the blocks detected by the detector.Type: GrantFiled: February 12, 2010Date of Patent: May 24, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Kazuya Kitsunai, Junji Yano
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Publication number: 20100313084Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.Type: ApplicationFiled: September 22, 2008Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Toshikatsu Hida, Shinichi Kanno, Hirokuni Yano, Kazuya Kitsunai, Shigehiro Asano, Junji Yano
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Publication number: 20100223424Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.Type: ApplicationFiled: May 12, 2010Publication date: September 2, 2010Inventors: KAZUYA KITSUNAI, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
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Publication number: 20100161885Abstract: A semiconductor storage device includes a first storage unit having a plurality of first blocks as data write regions; an instructing unit that issues a write instruction of writing data into the first blocks; a converting unit that converts an external address of input data to a memory position in the first block with reference to a conversion table in which external addresses of the data are associated with the memory positions of the data in the first blocks; and a judging unit that judges whether any of the first blocks store valid data associated with the external address based on the memory positions of the input data, wherein the instructing unit issues the write instruction of writing the data into the first block in which the valid data is not stored, when any of the first blocks does not store the valid data.Type: ApplicationFiled: September 8, 2009Publication date: June 24, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Shinichi KANNO, Shigehiro Asano, Kazuya Kitsunai, Hirokuni Yano, Toshikatsu Hida