Patents by Inventor Kazuya Nakayama

Kazuya Nakayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8422270
    Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: April 16, 2013
    Assignees: Sharp Kabushiki Kaisha, National University Corporation Kanazawa University
    Inventors: Suguru Kawabata, Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Nobuyoshi Awaya, Akio Kitagawa, Kazuya Nakayama
  • Publication number: 20120014541
    Abstract: An amplifying device for a condenser-microphone according to the present invention includes: a differential amplifier (20) having an inverting input terminal (1) to which a sound pressure signal output from a condenser microphone (21) is input and a non-inverting input terminal (2) to which a dc bias voltage is applied; a capacitor (24) connected between an output terminal (3) of the differential amplifier (20) and the inverting input terminal (1) of the differential amplifier (20); a resistive element (23) connected, in parallel with the capacitor (24), between the output terminal (3) of the differential amplifier (20) and the inverting input terminal (1) of the differential amplifier (20); and an ESD protecting element (25) having bidirectional diode characteristics, the ESD protecting element (25) being connected, in parallel with the capacitor (24), between the output terminal (3) of the differential amplifier (20) and the inverting input terminal (1) of the differential amplifier (20).
    Type: Application
    Filed: September 3, 2010
    Publication date: January 19, 2012
    Inventors: Kazuya Nakayama, Shigeo Masai
  • Publication number: 20110228586
    Abstract: A nonvolatile semiconductor memory device includes a bit voltage adjusting circuit which, for each bit line, fixes potentials of a selected bit line and a non-selected bit line to a predetermined potential to perform a memory operation and a data voltage adjusting circuit which, for each data line, fixes potentials of a selected data line and a non-selected data line to a predetermined potential to perform a memory operation. Each of the voltage adjusting circuits includes an operational amplifier and a transistor, a voltage required for a memory operation is input to the non-inverted input terminal of the operational amplifier, and the inverted input terminal of the operational amplifier is connected to the bit line or the data line, so that the potential of the bit line or the data line is fixed to a potential of the non-inverted input terminal of the operational amplifier.
    Type: Application
    Filed: March 10, 2011
    Publication date: September 22, 2011
    Inventors: Suguru KAWABATA, Shinobu Yamazaki, Yoshiji Ohta, Kazuya Ishihara, Nobuyoshi Awaya, Akio Kitagawa, Kazuya Nakayama
  • Patent number: 8008715
    Abstract: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the f
    Type: Grant
    Filed: August 4, 2008
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yusuke Kawaguchi, Kazuya Nakayama, Tsuyoshi Ohta, Takeshi Uchihara, Takahiro Kawano, Yuji Kato
  • Patent number: 7868883
    Abstract: There is provided an electro-optical circuit including: a substrate; a plurality of data lines and a plurality of scan lines disposed in a pixel region on the substrate to intersect each other; a plurality of pixel portions disposed at intersections of the data lines and the scan lines; a scan line driver circuit which applies scan signals through the scan lines to the pixel portions; an image signal apply circuit which applies image signals through the data lines to the a plurality of the pixel portions; and a plurality of power supply lines used to supply multiple-system powers to at least one of the scan line driver circuit and the image signal apply circuit.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: January 11, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Hiroaki Mochizuki, Kazuya Nakayama
  • Publication number: 20090032875
    Abstract: There is provided a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on the first semiconductor layer of the first conductivity type; a semiconductor region of the first conductivity type selectively provided on a front surface portion of the second semiconductor layer of the second conductivity type; a first main electrode provided in contact with a surface of the semiconductor region; a second main electrode provided on a side of the first semiconductor layer of the first conductivity type, the side being opposite to the surface on which the second semiconductor layer of the second conductivity type is provided; a gate wiring provided on the second semiconductor layer of the second conductivity type around an element region in which the semiconductor region is provided; a trench penetrating the second semiconductor layer of the second conductivity type to reach the first semiconductor layer of the f
    Type: Application
    Filed: August 4, 2008
    Publication date: February 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yusuke KAWAGUCHI, Kazuya Nakayama, Tsuyoshi Ohta, Takeshi Uchihara, Takahiro Kawano, Yuji Kato
  • Patent number: 7341900
    Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: March 11, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
  • Publication number: 20080035992
    Abstract: This semiconductor device comprises a drift layer of a first conductivity type formed on a drain layer of a first conductivity type, and a drain electrode electrically connected to the drain layer. A semiconductor base layer of a second conductivity type is formed in a surface of the drift layer, and a source region of a first conductivity type is further formed in the semiconductor base layer. A source electrode is electrically connected to the source region and a semiconductor base layer. Plural gate electrodes are formed through a gate insulation film so that a semiconductor base layer may be sandwiched by the gate electrodes. The width of the semiconductor base layer sandwiched by the gate electrodes is 0.3 micrometers or less.
    Type: Application
    Filed: August 9, 2007
    Publication date: February 14, 2008
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yusuke KAWAGUCHI, Yoshihiro Yamaguchi, Syotaro Ono, Akio Nakagawa, Miwako Akiyama, Kazuya Nakayama, Masakazu Yamaguchi
  • Publication number: 20060267913
    Abstract: There is provided an electro-optical circuit including: a substrate; a plurality of data lines and a plurality of scan lines disposed in a pixel region on the substrate to intersect each other; a plurality of pixel portions disposed at intersections of the data lines and the scan lines; a scan line driver circuit which applies scan signals through the scan lines to the pixel portions; an image signal apply circuit which applies image signals through the data lines to the a plurality of the pixel portions; and a plurality of power supply lines used to supply multiple-system powers to at least one of the scan line driver circuit and the image signal apply circuit.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 30, 2006
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Hiroaki MOCHIZUKI, Kazuya NAKAYAMA
  • Patent number: 7034346
    Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
  • Patent number: 7019361
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: January 19, 2005
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20050258503
    Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.
    Type: Application
    Filed: July 22, 2005
    Publication date: November 24, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
  • Patent number: 6958514
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Grant
    Filed: April 3, 2003
    Date of Patent: October 25, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20050121718
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Application
    Filed: January 19, 2005
    Publication date: June 9, 2005
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20040046202
    Abstract: A semiconductor device comprises a semiconductor substrate, a semiconductor layer formed above the semiconductor substrate, a plurality of unit cells each having a structure with a gate electrode disposed and formed above the semiconductor layer to have a stripe-like shape and with a source layer and a drain layer formed in the semiconductor layer to have stripe-like shapes respectively, a gate wiring line for mutually connecting together respective gate electrodes of the unit cells, a first main electrode being formed on a dielectric film covering the gate electrodes and the gate wiring line and being in contact with any one of the source layer and the drain layer of each unit cell, an impurity diffusion layer formed in the semiconductor layer to a depth reaching the semiconductor substrate only at part immediately underlying the gate wiring line, the part being selected from part immediately underlying a remaining one of the source layer and the drain layer of each unit cell and part immediately underlying
    Type: Application
    Filed: April 3, 2003
    Publication date: March 11, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Bungo Tanaka, Nobuyuki Sato
  • Publication number: 20040007766
    Abstract: A semiconductor device according to an embodiment of the present invention has a gate electrode which is formed on a semiconductor substrate via a gate insulating film, and which has a slit portion; side wall films formed at both side faces of the gate electrode and at side walls of the slit portion, and which fill an interior of the slit portion and cover the gate insulating film directly beneath the slit portion; and an interlayer insulating film formed to cover the gate electrode and the side wall films.
    Type: Application
    Filed: May 28, 2003
    Publication date: January 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Nakayama, Satoshi Aida, Shigeo Kouzuki, Masaru Izumisawa
  • Patent number: 6469425
    Abstract: An electron emission film includes a matrix consisting essentially of amorphous carbon and fullerene-like structures consisting essentially of a two-dimensional network of six-membered carbon rings. The fullerene-like structures are dispersed in the matrix and partially project from the matrix. The weight ratio of amorphous carbon to the fullerene-like structures is about 50:50 to 5:95. Amorphous carbon contains nitrogen acting as a donor at a concentration of about 4×10−7 to 10 atom %.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: October 22, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Kazuya Nakayama, Li Zhang, Gehan Anil Joseph Amaratunga, Ioannis Alexandrou, Mark Baxendale, Nalin Rupasinghe
  • Patent number: 6323831
    Abstract: An electron emitting comprising an emitter electrode for emitting electrons when applied with an electric field, a gate electrode for extracting the electrons emitted from the emitter electrode, when applied with a voltage from a signal source, the voltage being positive with respect to the emitter electrode, an anode electrode connected to a load, for collecting the electrons extracted by the gate electrode, and for passing an anode current, and a gate resistor connected between the signal source and the gate electrode, for reducing a gate current flowing in the gate electrode, without changing an anode current flowing in the anode, and for lowering a gate voltage by utilizing a voltage drop cause by the gate current.
    Type: Grant
    Filed: September 15, 1998
    Date of Patent: November 27, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomio Ono, Tadashi Sakai, Naoshi Sakuma, Kazuya Nakayama
  • Patent number: RE40705
    Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg [F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vt?Voff|?0.5·Cg·Rg·(dV/dt).
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Koichi Sugiyama
  • Patent number: RE40712
    Abstract: A high-breakdown-voltage semiconductor apparatus is provided, wherein when a gate capacitance of that portion of a gate electrode, under which a channel is formed, is Cg[F], a resistance in a channel length direction of that portion of the gate electrode, under which the channel is formed, is Rg [?], a threshold voltage, which is to be applied to the gate electrode and application of which permits flow of a drain current, is Vth [V], a voltage to be applied to the gate electrode to cut off the drain current is Voff [V], and a ratio of increase in the drain voltage per unit time at the time of cutting off the drain current is dV/dt [V/s], the following condition is satisfied: |Vth?Voff|?0.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: May 19, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nakayama, Koichi Sugiyama