Patents by Inventor Kazuyoshi Asada

Kazuyoshi Asada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200216002
    Abstract: A power supply system having a plurality of power systems is provided with a power output section in each of the power systems, an electrical load in each of the power systems, operating from power supplied by the power output section, main paths that connect the power output sections of adjacent ones of the power systems, an inter-system switch that establishes a conducting condition between the adjacent power systems by being turned on and establishes a disconnected condition between the adjacent power systems by being turned off, and an intra-system switch in each of the power systems, which is disposed on the main path between the power output section and the inter-system switch, and which establishes a conducting condition between the power output section and the electrical load by being turned on and establishes a disconnected condition between the power output section and the electrical load by being turned off.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: DENSO CORPORATION
    Inventors: Koji MAZAKI, Kazuyoshi OBAYASHI, Tadatoshi ASADA
  • Publication number: 20030120561
    Abstract: A menu displaying system and method is provided that can display timely information about articles recommended to customers by the shop side and quickly information about articles required by the customer. In the input terminal 10, when the input section 12 receives article information, the controller 13 transmits an update request, which requests updating the reference information database 32A in the server 30, and the article information, to the server 30. In response to the update request and the article information, the controller 33 in the server 30 updates the reference information database 32A in the storage 32, based on the article information, according to the reference information data creation program 32B. In the ordering terminal 20, the controller 23 transmits the order information and the customer information input to the input section 22, to the server 30.
    Type: Application
    Filed: December 23, 2002
    Publication date: June 26, 2003
    Applicant: NEC CORPORATION
    Inventor: Kazuyoshi Asada
  • Patent number: 5757287
    Abstract: An object recognition system using the image processing in which an area having a unique feature is extracted from an input image of an object, the unique image is registered in a shade template memory circuit as a shade template, the input image is searched for an image similar to the shade template registered by a shade pattern matching circuit, the position of an object is determined for each template, the speed and direction of movement of the object is determined from the positional information, and the results thereof are integrated by a separation/integration circuit, thereby recognizing the whole of the moving object.
    Type: Grant
    Filed: January 11, 1996
    Date of Patent: May 26, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Tadaaki Kitamura, Yoshiki Kobayashi, Kunio Nakanishi, Masakazu Yahiro, Yoshiyuki Satoh, Toshiro Shibata, Takeshi Horie, Katsuyuki Yamamoto, Masao Takatoo, Haruki Inoue, Kazuyoshi Asada
  • Patent number: 5554983
    Abstract: An object recognition system using the image processing in which an area having a unique feature is extracted from an input image of an object, the unique image is registered in a shade template memory circuit as a shade template, the input image is searched for an image similar to the shade template registered by a shade pattern matching circuit, the position of an object is determined for each template, the speed and direction of movement of the object is determined from the positional information, and the results thereof are integrated by a separation/integration circuit, thereby recognizing the whole of the moving object.
    Type: Grant
    Filed: April 23, 1993
    Date of Patent: September 10, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Tadaaki Kitamura, Yoshiki Kobayashi, Kunio Nakanishi, Masakazu Yahiro, Yoshiyuki Satoh, Toshiro Shibata, Takeshi Horie, Katsuyuki Yamamoto, Masao Takatoo, Haruki Inoue, Kazuyoshi Asada
  • Patent number: 5295197
    Abstract: An information processing apparatus using a neural network learning function has, in one embodiment, a computer system and a pattern recognition apparatus associated with each other via a communication cable. The computer system includes a learning section having a first neural network and serves to adjust the weights of connection therein as a result of learning with a learning data signal supplied thereto from the pattern recognition apparatus via the communication cable. The pattern recognition apparatus includes an associative output section having a second neural network and receives data on the adjusted weights from the learning section via the communication cable to reconstruct the second neural network with the data on the adjusted weights. The pattern recognition apparatus with the associative output section having the reconstructed second neural network performs pattern recognition independently of the computer system with the communication cable being brought into an electrical isolation mode.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: March 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Takenaga, Yoshiyuki Okuyama, Masao Takatoo, Kazuyoshi Asada, Norio Tanaka, Tadaaki Kitamura, Kuniyuki Kikuchi
  • Patent number: 5274717
    Abstract: An LSI parallel image processor in which line buffers and data-flow switching circuits each requiring a larger amount of hardware in the prior art are incorporated into an LSI circuit, the image data delayed by the line buffers is output from an image data output port, shift registers each having a variable number of steps for preserving local image regions are intermittently shifted-in in accordance with applied clocks, and the contents of the shift registers are sequentially read out.
    Type: Grant
    Filed: October 20, 1992
    Date of Patent: December 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Shuuichi Miura, Yoshiki Kobayashi, Tadashi Fukushima, Yoshiyuki Okuyama, Takeshi Katoh, Kotaro Hirasawa, Kazuyoshi Asada
  • Patent number: 5086479
    Abstract: An information processing apparatus using a neural network learning function has, in one embodiment, a computer system and a pattern recognition apparatus associated with each other via a communication cable. The computer system includes a learning section having a first neural network and serves to adjust the weights of connection therein as a result of learning with a learning data signal supplied thereto from the pattern recognition apparatus via the communication cable. The pattern recognition apparatus includes an associative output section having a second neural network and receives data on the adjusted weights from the learning section via the communication cable to reconstruct the second neural network with the data on the adjusted weights. The pattern recognition apparatus with the associative output section having the reconstructed second neural network performs pattern recognition independently of the computer system with the communication cable being brought into an electrical isolation mode.
    Type: Grant
    Filed: June 28, 1990
    Date of Patent: February 4, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hiroshi Takenaga, Yoshiyuki Okuyama, Masao Takatoo, Kazuyoshi Asada, Norio Tanaka, Tadaaki Kitamura, Kuniyuki Kikuchi
  • Patent number: 4344129
    Abstract: A data processor system is capable of operating in a first mode comprising a computer mode so as to carry out data processing functions and is also capable of operating in a second mode comprising a sequencer mode so as to carry out high speed sequence operations on the basis of programmed sequences. A high speed change between the computer and sequencer modes can freely be effected by executing mode change instructions so that the data processor system performs the duplex functions of a computer and a sequencer.
    Type: Grant
    Filed: August 16, 1979
    Date of Patent: August 10, 1982
    Assignee: Hitachi, Ltd.
    Inventors: Kazuyoshi Asada, Hajime Yasuda, Kunihiko Ohnuma
  • Patent number: 4339794
    Abstract: Novel method and system for controlling input/output in a process control wherein state signals of object processes to be controlled are applied to a CPU via a process input/output unit and operated in the CPU in accordance with a logic programmed and stored in advance, and results of the operation are delivered out to the object processes to control the same. A buffer memory is interposed between the CPU and the process input/output unit. While reception and delivery of data are performed between the CPU or processor unit and the buffer memory, fetching of the state signals of the object processes or delivery of the process controlling signals is performed between the buffer memory and the object processes, thereby attaining a high rate processing as viewed from the overall processing of the system.
    Type: Grant
    Filed: September 12, 1979
    Date of Patent: July 13, 1982
    Assignees: Hitachi, Ltd., Nissan Motor Co, Ltd.
    Inventors: Keiji Hideshima, Haruo Koyanagi, Shuichi Senda, Kazuyoshi Asada, Norio Murayama, Yoshiyuki Nihashi, Masaoki Takaki
  • Patent number: 4326207
    Abstract: A sequence control system includes a main memory unit for storing therein a sequence program, an operation and control unit for decoding the sequence instruction and executing the designated operations, an input unit for fetching states of a process to be controlled as inputs, and an output unit for producing an output signal to control the process.
    Type: Grant
    Filed: April 14, 1980
    Date of Patent: April 20, 1982
    Assignees: Hitachi, Ltd., Nissan Motor Co., Ltd.
    Inventors: Hiroharu Suda, Keiji Hideshima, Kazuyoshi Asada, Masaoki Takaki, Isao Yasuda, Atsutaro Kamei
  • Patent number: 4316260
    Abstract: A programmable sequence controller is provided with a display signal processor for preparing and correcting a sequence program in combination with a CRT (or cathode ray tube) display device. The signal processor simply effects signal processing of branch points and composition points in case where a so-called "ladder diagram" constituting the sequence diagram with relay symbols is prepared and displayed. Branch information is stored in an FIFO (or first in first out) register. The branch information is sequentially received and stored, and the information thus stored is read out in the order of storage, thus preparing the ladder diagram. There are provided a register for instructing the FI operation and a register for instructing the FO operation. The sequence display controller is applicable to the cases where a new ladder diagram is to be prepared, the diagram once prepared is corrected, and the operation is checked.
    Type: Grant
    Filed: September 13, 1979
    Date of Patent: February 16, 1982
    Assignees: Hitachi, Ltd., Nissan Motor Co., Ltd.
    Inventors: Keiji Hideshima, Haruo Koyanagi, Hiroharu Suda, Hirokazu Sawano, Masaoki Takaki, Kunio Yamanaka, Isao Yasuda, Kazuyoshi Asada
  • Patent number: 4298958
    Abstract: A sequence control system suitable for checking the operation of an information processor includes a process I/O unit for receiving input data from process inputs and providing output data to process outputs; a sequence processing unit for calculating data at the process outputs by performing sequence operations according to the sequence programs stored in a sequence program memory on the basis of the data at the process inputs; a buffer memory provided between the process I/O unit and the sequence processing unit for storing both the process input data from the process I/O unit and the output data from the sequence processing unit; a control arrangement for setting the input data to the buffer memory and for allowing access to a selected sequence program according to manually set input information; a display for displaying the selected sequence program accessed through the control arrangement; and a switch for interrupting the transfer of I/O data between the process I/O unit and the buffer memory.
    Type: Grant
    Filed: September 7, 1979
    Date of Patent: November 3, 1981
    Assignees: Hitachi, Ltd., Nissan Motor Co., Ltd.
    Inventors: Masaoki Takaki, Hirokazu Sawano, Kunio Yamanaka, Kazuyoshi Asada, Keiji Hideshima, Haruo Koyanagi