Patents by Inventor Kazuyoshi Ueno
Kazuyoshi Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240125669Abstract: A vibration control device, while applying Gaussian vibration that matches a target vibration physical quantity PSD to a test piece, makes a corresponding vibration physical quantity non-Gaussian. Using a response vibration physical quantity PSD and a target vibration physical quantity PSD, a control vibration physical quantity PSD calculation generates a control vibration physical quantity PSD for generating a drive signal. A PSD conversion converts the control vibration physical quantity PSD into a control corresponding vibration physical quantity PSD of another dimension. Using the control corresponding vibration physical quantity PSD, a control corresponding vibration physical quantity waveform calculation calculates a control corresponding vibration physical quantity waveform that is non-Gaussian.Type: ApplicationFiled: November 28, 2023Publication date: April 18, 2024Inventors: Kazuyoshi UENO, Yoshikado YAMAUCHI, Yuji NAKAURA
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Patent number: 11879816Abstract: A vibration control device, while applying Gaussian vibration that matches a target vibration physical quantity PSD to a test piece, makes a corresponding vibration physical quantity non-Gaussian. Using a response vibration physical quantity PSD and a target vibration physical quantity PSD, a control vibration physical quantity PSD calculation generates a control vibration physical quantity PSD for generating a drive signal. A PSD conversion converts the control vibration physical quantity PSD into a control corresponding vibration physical quantity PSD of another dimension. Using the control corresponding vibration physical quantity PSD, a control corresponding vibration physical quantity waveform calculation calculates a control corresponding vibration physical quantity waveform that is non-Gaussian.Type: GrantFiled: October 21, 2019Date of Patent: January 23, 2024Assignee: IMV CORPORATIONInventors: Kazuyoshi Ueno, Yoshikado Yamauchi, Yuji Nakaura
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Publication number: 20210356352Abstract: A vibration control device, while applying Gaussian vibration that matches a target vibration physical quantity PSD to a test piece, makes a corresponding vibration physical quantity non-Gaussian. Using a response vibration physical quantity PSD and a target vibration physical quantity PSD, a control vibration physical quantity PSD calculation generates a control vibration physical quantity PSD for generating a drive signal. A PSD conversion converts the control vibration physical quantity PSD into a control corresponding vibration physical quantity PSD of another dimension. Using the control corresponding vibration physical quantity PSD, a control corresponding vibration physical quantity waveform calculation calculates a control corresponding vibration physical quantity waveform that is non-Gaussian.Type: ApplicationFiled: October 21, 2019Publication date: November 18, 2021Inventors: Kazuyoshi UENO, Yoshikado YAMAUCHI, Yuji NAKAUARA
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Patent number: 8784931Abstract: A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer and an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, a SiO2 surface of the insulating interlayer portion on which the diffusion layer is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. A capping layer may be formed on the wiring layer by electroless plating. Consequently, a diffusion prevention layer having good adhesive properties can be formed through a simple wet process, and, the wiring layer can directly be formed on this diffusion prevention layer by a wet process. The capping layer can also be directly formed on the wiring layer by electroless plating.Type: GrantFiled: September 23, 2009Date of Patent: July 22, 2014Assignees: Waseda University, Renesas Electronics CorporationInventors: Kazuyoshi Ueno, Tetsuya Osaka, Nao Takano
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Patent number: 8069728Abstract: Focusing on the criterion of “Energy save” or “Quiet noise” or other suitable operating parameter and considering the existing limitation of the operation of the electro-dynamic shaker system, apparatus for optimizing the operating condition of the vibration test system is proposed. The apparatus 100 measures the field current and drive current under the state that the desired vibration is fed to the specimen 20, and calculates the necessary force the shaker 1 should supply. Field current is supposed to be varied, and the necessary drive current is calculated based on the necessary force data. Further, the blower rotation is supposed to be varied, and the total power consumption at the coils and the blower is calculated. Also the temperatures of the field coil 4 and of the drive coil 10 is estimated and checked whether within the limitation. Then the optimal operating condition for the focused criterion is selected.Type: GrantFiled: October 2, 2008Date of Patent: December 6, 2011Assignee: IMV CorporationInventors: John Goodfellow, Kazuyoshi Ueno, Milan Prodanovic, Koshi Yamamoto, Norihiro Maeda
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Patent number: 7821135Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.Type: GrantFiled: May 9, 2005Date of Patent: October 26, 2010Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno
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Patent number: 7741214Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.Type: GrantFiled: December 1, 2008Date of Patent: June 22, 2010Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Kazuyoshi Ueno
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Publication number: 20100006326Abstract: A method of manufacturing ULSI wiring in which wiring layers are separately formed via a diffusion prevention layer with an insulating interlayer portion made of SiO2. The method comprises the steps of treating, with a silane compound, an SiO2 surface on which the insulating interlayer portion is to be formed, performing catalyzation with an aqueous solution containing a palladium compound, forming the diffusion prevention layer by electroless plating, and then forming the wiring layer on this diffusion prevention layer. Furthermore, a capping layer is formed on the wiring layer by electroless plating. Consequently, the diffusion prevention layer having good adhesive properties can all be formed through a simple process by wet processes, and further, the wiring layer can directly be formed on this diffusion prevention layer by the wet process. In addition, the capping layer can directly be formed on this wiring layer by electroless plating.Type: ApplicationFiled: September 23, 2009Publication date: January 14, 2010Applicants: NEC ELECTRONICS CORPORATION, WASEDA UNIVERSITYInventors: Kazuyoshi Ueno, Tetsuya Osaka, Nao Takano
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Publication number: 20090258481Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.Type: ApplicationFiled: March 27, 2009Publication date: October 15, 2009Inventor: Kazuyoshi Ueno
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Publication number: 20090205430Abstract: Focusing on the criterion of “Energy save” or “Quiet noise” or other suitable operating parameter and considering the existing limitation of the operation of the electro-dynamic shaker system, apparatus for optimizing the operating condition of the vibration test system is proposed. The apparatus 100 measures the field current and drive current under the state that the desired vibration is fed to the specimen 20, and calculates the necessary force the shaker 1 should supply. Field current is supposed to be varied, and the necessary drive current is calculated based on the necessary force data. Further, the blower rotation is supposed to be varied, and the total power consumption at the coils and the blower is calculated. Also the temperatures of the field coil 4 and of the drive coil 10 is estimated and checked whether within the limitation. Then the optimal operating condition for the focused criterion is selected.Type: ApplicationFiled: October 2, 2008Publication date: August 20, 2009Applicant: IMV CORPORATIONInventors: John GOODFELLOW, Kazuyoshi UENO, Milan PRODANOVIC, Koshi YAMAMOTO, Norihiro MAEDA
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Patent number: 7566973Abstract: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S100); forming a barrier metal layer on the whole surface of the insulating film (S102); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S104); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S106); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S108); and flattening the cap metal layer by polishing (S110).Type: GrantFiled: July 20, 2006Date of Patent: July 28, 2009Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno
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Patent number: 7563696Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.Type: GrantFiled: March 22, 2007Date of Patent: July 21, 2009Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno
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Publication number: 20090081870Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.Type: ApplicationFiled: December 1, 2008Publication date: March 26, 2009Applicant: NEC ELECTRONICS CORPORATIONInventors: Toshiyuki Takewaki, Kazuyoshi Ueno
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Patent number: 7485566Abstract: A method of manufacturing a semiconductor device is provided. The method includes: (A) forming an insulating film with a porous structure on a substrate; (B) forming a trench in the insulating film, the trench being used for forming an interconnection; (C) depositing a metal layer over the insulating film such that the trench is filled in with the metal layer; (D) forming the interconnection by removing an excess metal layer outside the trench; (E) modifying a surface of the insulating film to form a modified layer on the insulating film; and (F) forming a metal film selectively on the interconnection by using plating solution after the (E) modifying process.Type: GrantFiled: October 6, 2006Date of Patent: February 3, 2009Assignee: NEC Electronics CorporationInventors: Naoyoshi Kawahara, Kazuyoshi Ueno
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Patent number: 7479700Abstract: In a semiconductor device, an insulating interlayer is provided above a semiconductor substrate, and a plurality of first wiring layers and a plurality of second wiring layers are formed in the insulating interlayer. The first wiring layers are substantially composed of copper, and are arranged in parallel at a large pitch. The second wiring layers are substantially composed of copper, and are arranged in parallel at a small pitch. A first metal capping layer is formed on each of the first wiring layers, and a second metal capping layer is formed on each of the second wiring layers. The second metal capping layer has a smaller thickness than that of the first metal capping layer.Type: GrantFiled: January 5, 2006Date of Patent: January 20, 2009Assignee: NEC Electronics CorporationInventors: Toshiyuki Takewaki, Kazuyoshi Ueno
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Patent number: 7332813Abstract: A semiconductor device with a metallic region can have a resistance to stress migration and increased reliability. A lower layer wiring made from a barrier metal film (102) and a copper containing metallic film (103) can be formed within an insulating film (101). An interlayer insulating film (104 or 104a and 104b) can be formed thereon. An upper layer wiring made from a barrier metal film (106 or 106a and 106b) and a copper containing metallic film (111 or 111a and 111b) is formed within the interlayer insulating film (104 or 104a and 104b). A silver containing metallic protective film (108a and 108b) can be formed on surfaces of the lower layer wiring and upper layer wiring.Type: GrantFiled: June 30, 2003Date of Patent: February 19, 2008Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno
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Publication number: 20070245828Abstract: Disclosed is a vibration test method for evaluating the vibration resistance of a specimen, comprising a test specification setting step (S10) of determining reference vibration conditions for the specimen based on transport conditions during actual transportation; a reference value attainment step (S20) of calculating an amplitude level and a reference accumulated fatigue value of the specimen under the reference vibration conditions; a test condition determination step (S30) of determining test vibration conditions and a test time based on an allowable amplification factor of the amplitude level and a desired vibration time, so that an accumulated fatigue value which is calculated from the vibration detection value of the specimen satisfies the reference accumulated fatigue value; and a vibration-imparting step (S40) of vibrating the specimen based on the test vibration conditions and the test time.Type: ApplicationFiled: December 18, 2006Publication date: October 25, 2007Applicants: OSAKA PREFECTURAL GOVERNMENT, IMV CORPORATIONInventors: Takamasa Nakajima, Kazuki Tsuda, Zenji Sakai, Kazuyoshi Ueno, Masakazu Shirahoshi, Koji Kawata, Yoshikado Yamauchi
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Patent number: 7259095Abstract: A semiconductor device of improved stress-migration resistance and reliability includes an insulating film having formed therein a lower interconnection consisting of a barrier metal film and a copper-silver alloy film, on which is then formed an interlayer insulating film. In the interlayer insulating film is formed an upper interconnection consisting of a barrier metal film and a copper-silver alloy film. The lower and the upper interconnections are made of a copper-silver alloy which contains silver in an amount more than a solid solution limit of silver to copper.Type: GrantFiled: February 24, 2005Date of Patent: August 21, 2007Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno
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Publication number: 20070161128Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.Type: ApplicationFiled: March 22, 2007Publication date: July 12, 2007Inventor: Kazuyoshi UENO
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Patent number: 7220318Abstract: A semiconductor device manufacturing apparatus which uses a thermal CVD reaction to deposit a film onto a substrate has a ring with an electrode terminal that makes contact with either the substrate or the deposited film thereon, a power supply that applies a current or a potential to this electrode terminal of the ring, and a piston cylinder mechanism for moving the ring up and down, so as to cause its electrode terminal to make and break contact with the substrate or deposited film thereon.Type: GrantFiled: July 24, 2003Date of Patent: May 22, 2007Assignee: NEC Electronics CorporationInventor: Kazuyoshi Ueno