Patents by Inventor Kazuyuki Imamura
Kazuyuki Imamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446020Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.Type: GrantFiled: October 12, 2010Date of Patent: May 21, 2013Assignees: Fujitsu Limited, Fujitsu Semiconductor LimitedInventors: Masateru Koide, Daisuke Mizutani, Aiichiro Inoue, Hideo Yamashita, Iwao Yamazaki, Masayuki Kato, Seiji Ueno, Kazuyuki Imamura
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Publication number: 20110089579Abstract: A multi-chip module includes: a board; a wiring board disposed on the board and including a wiring pattern; and a plurality of chips disposed on the wiring board. Each of the plurality of chips is connected with at least one of the other chips, and the plurality of chips and the board are electrically connected with each other via a portion other than the wiring pattern of the wiring board.Type: ApplicationFiled: October 12, 2010Publication date: April 21, 2011Applicants: FUJITSU LIMITED, FUJITSU SEMICONDUCTOR LIMITEDInventors: Masateru KOIDE, Daisuke MIZUTANI, Aiichiro INOUE, Hideo YAMASHITA, Iwao YAMAZAKI, Masayuki KATO, Seiji UENO, Kazuyuki IMAMURA
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Patent number: 7754534Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: GrantFiled: April 21, 2008Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20100155941Abstract: A semiconductor device includes multiple electrode pads provided in an interconnection layer over a semiconductor substrate; an insulating layer provided on the interconnection layer so as to expose portions of the electrode pads; multiple conductive layers having their respective first ends connected to the exposed portions of the corresponding electrode pads so as to extend therefrom on the insulating layer; and multiple protruding electrodes provided at respective second ends of the conductive layers, wherein the conductive layers extend in a given direction relative to the electrode pads.Type: ApplicationFiled: January 20, 2010Publication date: June 24, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hirohisa Matsuki, Kazuyuki Imamura
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Publication number: 20090297645Abstract: The present invention relates to a fibroblast activator comprising grape sap as an active ingredient, a method of activating a fibroblast, using grape sap, and a method of using grape sap as a fibroblast activator. The present invention further relates to a collagen synthesis promoter comprising grape sap as an active ingredient, a method of promoting collagen synthesis using grape sap, and a method of using grape sap as a collagen synthesis promoter. The present invention further relates to a skin antiaging agent comprising grape sap as an active ingredient, a method of preventing aging of skin using grape sap, and a method of using grape sap as a skin antiaging agent. The present invention provides highly safe and effective means of preventing aging.Type: ApplicationFiled: October 17, 2006Publication date: December 3, 2009Inventors: Azuma Watanabe, Kazuyuki Imamura
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Patent number: 7483818Abstract: A structural analysis program which enables easy structural analysis in accordance with a finite element method based on data representing a two-dimensional shape. A two-dimensional model of a structure is produced in response to a manipulation input which designates a material arrangement pattern and a thickness of each layer of the structure. A three-dimensional model is produced by adding the designated thickness of each layer to the material arrangement pattern of the layer so as to make the material arrangement pattern three-dimensional and stacking the three-dimensionalized material arrangement pattern of each layer. A finite element model is produced by dividing the three-dimensional model into a plurality of voxels. The computer performs structural analysis based on the produced finite element model. Thereby, an analysis result of a multilayer structure defined by the two-dimensional model is obtained.Type: GrantFiled: May 31, 2002Date of Patent: January 27, 2009Assignee: Fujitsu Nagano Systems Engineering LimitedInventors: Makoto Amakai, Iwao Sugiura, Takanori Negishi, Yasuhiro Kawashima, Gen Kamurai, Kazuyuki Imamura
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Publication number: 20080261336Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: April 21, 2008Publication date: October 23, 2008Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 7268433Abstract: A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.Type: GrantFiled: October 24, 2005Date of Patent: September 11, 2007Assignee: Fujitsu LimitedInventors: Yoshihiro Matsuoka, Kazuyuki Imamura, Masao Oshima, Takashi Suzuki, Toyoji Sawada
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Publication number: 20070001317Abstract: A wiring layer is provided on a semiconductor substrate and extends in a predetermined direction. An external connection electrode terminal is provided on the wiring layer through a plurality of column-shaped conductors. The column-shaped conductors are located under the external connection electrode terminal. A density of arrangement of the column-shaped conductors is varied according to a direction of extension of the wiring layer.Type: ApplicationFiled: October 24, 2005Publication date: January 4, 2007Applicant: FUJITSU LIMITEDInventors: Yoshihiro Matsuoka, Kazuyuki Imamura, Masao Oshima, Takashi Suzuki, Toyoji Sawada
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Patent number: 6875638Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: GrantFiled: March 19, 2002Date of Patent: April 5, 2005Assignee: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Publication number: 20040232549Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: June 29, 2004Publication date: November 25, 2004Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 6796025Abstract: In a method for mounting an electronic part on a mounting substrate in that projection electrodes provided on the electronic part are welded by fusion to join connection terminals provided on the mounting substrate, the flux paste includes a base flux and metal grains having diameters smaller than the diameters of projection electrodes and having a thickness so as to form a space between the flux paste and the electronic part when the electronic part is mounted on the mounting substrate and the flux paste is arranged on the mounting substrate. A resin is sealed in the space formed between the electronic part and the mounting substrate after the projection electrodes are joined to the connection terminals.Type: GrantFiled: February 28, 2002Date of Patent: September 28, 2004Assignee: Fujitsu LimitedInventors: Kazuyuki Imamura, Osamu Yamaguchi, Yasunori Fujimoto, Toshiya Akamatsu
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Patent number: 6794273Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: GrantFiled: December 31, 2002Date of Patent: September 21, 2004Assignee: Fujitsu LimitedInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Publication number: 20040053444Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: ApplicationFiled: August 29, 2003Publication date: March 18, 2004Applicant: FUJITSU LIMITEDInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Publication number: 20030219969Abstract: A method of manufacturing a semiconductor device using a wiring substrate is provided which can facilitate the handling of the wiring substrate. The method includes the steps of forming a peelable resin layer on a silicon substrate, forming the wiring substrate on the peelable resin layer, mounting semiconductor chips on the wiring substrate, forming semiconductor devices by sealing the plurality of semiconductor chips by a sealing resin, individualizing the semiconductor devices by dicing the semiconductor devices from the sealing resin side but leaving the silicon substrate, peeling each of the individualized semiconductor devices from the silicon substrate between the silicon substrate and the peelable resin layer, and exposing terminals on the wiring substrate by forming openings through the peelable resin layer or by removing the peelable resin layer.Type: ApplicationFiled: December 31, 2002Publication date: November 27, 2003Applicant: FUJITSU LIMITEDInventors: Nobukatsu Saito, Masaharu Minamizawa, Yoshiyuki Yoneda, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Tadahiro Okamoto, Eiji Watanabe
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Patent number: 6566748Abstract: A BGA semiconductor device includes a package substrate carrying thereon a semiconductor chip in a face-down state and a cap member covering the semiconductor chip on the package substrate, wherein the cap member has a optimized Young modulus smaller than about 20 GPa and a thermal conductivity exceeding about 100 W/(m·K).Type: GrantFiled: July 13, 2000Date of Patent: May 20, 2003Assignee: Fujitsu LimitedInventors: Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaharu Minamizawa
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Publication number: 20030082846Abstract: A manufacturing method of a semiconductor device incorporating a passive element includes the steps as follows: a redistribution board forming step forms a redistribution board incorporating the passive element on a base board; a semiconductor element mounting step mounts at least one semiconductor element formed on an opposite side surface of the redistribution board with regard to the base board; a base board separating step separates the base board from the redistribution board and exposes the other surface of the redistribution board; a redistribution board mounting step mounts the redistribution board on a package board via electrode pads exposed from the other surface of the redistribution board.Type: ApplicationFiled: March 19, 2002Publication date: May 1, 2003Applicant: Fujitsu LimitedInventors: Yoshiyuki Yoneda, Masaharu Minamizawa, Nobutaka Shimizu, Kazuyuki Imamura, Atsushi Kikuchi, Masaru Nukiwa, Osamu Yamaguchi, Yasunori Fujimoto, Takumi Ihara, Muneharu Morioka, Yukihiro Kuriki, Masaki Uchida
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Publication number: 20030055612Abstract: A structural analysis program which enables easy structural analysis in accordance with a finite element method based on data representing a two-dimensional shape. A two-dimensional model of a structure is produced in response to a manipulation input which designates a material arrangement pattern and a thickness of each layer of the structure. A three-dimensional model is produced by adding the designated thickness of each layer to the material arrangement pattern of the layer so as to make the material arrangement pattern three-dimensional and stacking the three-dimensionalized material arrangement pattern of each layer. A finite element model is produced by dividing the three-dimensional model into a plurality of voxels. The computer performs structural analysis based on the produced finite element model. Thereby, an analysis result of a multilayer structure defined by the two-dimensional model is obtained.Type: ApplicationFiled: May 31, 2002Publication date: March 20, 2003Applicant: Fujitsu Nagano Systems Engineering LimitedInventors: Makoto Amakai, Iwao Sugiura, Takanori Negishi, Yasuhiro Kawashima, Gen Kamurai, Kazuyuki Imamura
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Publication number: 20020185309Abstract: In a method for mounting an electronic part on a mounting substrate in that projection electrodes provided on the electronic part are welded by fusion to join connection terminals provided on the mounting substrate, the flux paste includes a base flux and metal grains having diameters smaller than the diameters of projection electrodes and having a thickness so as to form a space between the flux paste and the electronic part when the electronic part is mounted on the mounting substrate and the flux paste is arranged on the mounting substrate. A resin is sealed in the space formed between the electronic part and the mounting substrate after the projection electrodes are joined to the connection terminals.Type: ApplicationFiled: February 28, 2002Publication date: December 12, 2002Applicant: Fujitsu LimitedInventors: Kazuyuki Imamura, Osamu Yamaguchi, Yasunori Fujimoto, Toshiya Akamatsu
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Patent number: 6476503Abstract: A semiconductor device including a semiconductor chip sealed with an encapsulating resin. Columnar electrodes are connected to electrode pads of the semiconductor chip, and extend through the encapsulating resin. The columnar electrodes are made from bonding wires and include enlarged outer ends. Solder balls are arranged on the surface of the encapsulating resin and connected to the outer ends of the columnar electrodes. In another example, pin wires are formed by half-cutting bonding wires, bonding one end of each of the bonding wires, and cutting the bonding wires at the half-cut portions.Type: GrantFiled: June 29, 2000Date of Patent: November 5, 2002Assignee: Fujitsu LimitedInventors: Kazuyuki Imamura, Yasunori Fujimoto, Masaaki Seki, Tetsuya Fujisawa, Mitsutaka Sato, Ryuji Nomoto, Junichi Kasai, Yoshitaka Aiba, Noriaki Shiba