Patents by Inventor Kazuyuki Kawauchi

Kazuyuki Kawauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor integrated circuit device having an improved arrangement of power source lines
    Patent number: 5008728
    Abstract: A semiconductor integrated circuit device includes a plurality of functional blocks each executing respective logic operations and arranged in an internal area on a semiconductor chip, and a first power source line arranged so as to surround the internal area. The first power source line is a closed-loop line. Second power source lines are provided for the respective functional blocks so as to surround the respective functional blocks on the chip. Each of the second power source lines is a closed-loop line. Third power source lines mutually connect the second power source lines for the functional blocks and connect the second power source lines and the first power source line.
    Type: Grant
    Filed: September 14, 1989
    Date of Patent: April 16, 1991
    Assignee: Fujitsu Limited
    Inventors: Takeshi Yamamura, Seiji Endo, Kazuyuki Kawauchi, Hiroki Korenaga
  • Semiconductor integrated circuit device having multilayer power supply lines
    Patent number: 4989062
    Abstract: A semiconductor integrated circuit device having multilayer power supply lines includes a plurality of power supply lines formed on a semiconductor chip for supplying power to the cells. The power supply lines are constructed by the multilayer structure having three different layer levels. First-level (lower) and third-level (upper) power supply lines are arranged in parallel so as to overlap each other. Second-level (intermittent) power supply lines are arranged in parallel so as to extend in a direction perpendicular to the first-level and third-level power supply lines. The overlapping first and third power supply lines are set at different potentials.
    Type: Grant
    Filed: June 16, 1988
    Date of Patent: January 29, 1991
    Assignee: Fujitsu Limited
    Inventors: Hiromasa Takahashi, Kazuyuki Kawauchi, Shigeru Fujii
  • Gate array integrated device having mixed single column type and matrix type arrays
    Patent number: 4661815
    Abstract: A gate array integrated device including a plurality of single column type arrays, a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the single column type arrays and the matrix type arrays. One of the single column type arrays facing at least one side of each of the matrix type arrays.
    Type: Grant
    Filed: October 2, 1985
    Date of Patent: April 28, 1987
    Assignee: Fujitsu Limited
    Inventors: Yoshihisa Takayama, Shigeru Fujii, Kazuyuki Kawauchi, Toshihiko Yoshida