Patents by Inventor Kazuyuki Miyazawa

Kazuyuki Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080300375
    Abstract: The present invention is an eye lens material wherein phosphorylcholine groups of a specific structure are covalently bonded onto the material surface by means of an after-treatment in which a phosphorylcholine-containing chemical compound is reacted with an eye lens material. The object of the present invention is to provide a contact lens that prevents protein adsorption and a method of manufacturing thereof.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 4, 2008
    Inventors: Yukimitsu Suda, Kazuyuki Miyazawa, Kazuhiko Ishihara
  • Publication number: 20080300369
    Abstract: The present invention is a method of manufacturing an eye lens material having a process in which a phosphorylcholine group-containing chemical compound represented by the following formula (1) is reacted and covalently bonded to the surface of an eye lens material having hydroxyl groups wherein the chemical compound represented by the following formula (2) is reacted and covalently bonded through ester-bonding to the eye lens material in an organic solvent. The object of the present invention is to provide an eye lens material that prevents protein adsorption and a method of manufacturing thereof.
    Type: Application
    Filed: May 18, 2005
    Publication date: December 4, 2008
    Inventors: Yukimitsu Suda, Kazuyuki Miyazawa, Kazuhiko Ishihara
  • Publication number: 20080214855
    Abstract: A phosphorylcholine group-containing chemical compound represented by the following formula (1). In this formula, m denotes 2-6 and n denotes 1-4. X1, X2, and X3, independent of each other, denote a methoxy group, ethoxy group, or halogen. Up to two of X1, X2, and X3 can be any of the following groups: a methyl group, ethyl group, propyl group, isopropyl group, butyl group, or isobutyl group. R is one of the structures in the following formulas (2)-(4) (the chemical compound of formula (1) in the structures of the following formulas (2)-(4) is expressed as A-R—B). In formulas (2)-(4), L is 1-6, P is 1-3. Also a surface modifier consisting of the aforementioned phosphorylcholine group-containing chemical compound, modified powder treated with said surface modifier, a chromatography packing consisting of a modified carrier treated with said surface modifier, a filter treated with said surface modifier, and a glass device treated with said surface modifier.
    Type: Application
    Filed: December 1, 2004
    Publication date: September 4, 2008
    Inventors: Yousuke Toujo, Kazuyuki Miyazawa, Taketoshi Kanda, Hiroshi Kutsuna, Kenichi Sakuma, Masayoshi Wada, Yukimitsu Suda
  • Publication number: 20080205111
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Application
    Filed: January 9, 2008
    Publication date: August 28, 2008
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20080113942
    Abstract: The present invention is a phosphorylcholine-containing chemical compound represented by the following formula (1) or (2). (CH3)3N+CH2CH2PO4?CH2COOH ??(1) (CH3)3N+CH2CH2PO4?CH2COONa ??(2) The object of the present invention is to provide a new phosphorylcholine-containing compound that is useful as a surface treatment agent or a source material of a surface treatment agent. Another object is to provide a manufacturing method that has a high industrial utility value.
    Type: Application
    Filed: November 28, 2005
    Publication date: May 15, 2008
    Inventors: Yukimitsu Suda, Kazuyuki Miyazawa
  • Patent number: 7348424
    Abstract: The present invention is a method for manufacturing a phosphorylcholine group-containing polysaccharide wherein the aldehyde derivative-containing compound obtained by the oxidative ring-opening reaction of glycerophosphorylcholine is added to a polysaccharide containing amino groups as well as a new polysaccharide having phosphorylcholine groups obtained from this manufacturing method. The object of the present invention is to provide a phosphorylcholine group-containing polysaccharide that is superior in biocompatibility and moisture retention, and is useful as a polymer material for medical use, as well as a simple method of manufacturing it. The polysaccharide of the present invention is utilized, for example, in artificial organs, biomembranes, coating agents for medical tools, drug delivery, and in cosmetics.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: March 25, 2008
    Assignee: Shiseido Company, Ltd.
    Inventors: Kazuyuki Miyazawa, Toshio Yanaki, Francoise M. Winnik
  • Patent number: 7345929
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: March 18, 2008
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20080038221
    Abstract: The present invention is a method of manufacturing an eye lens material having a process in which a phosphorylcholine group-containing chemical compound represented by the following formula (1) is reacted and covalently bonded onto the surface of an eye lens material wherein a chemical compound having an end amino group is introduced to said eye lens material and then the chemical compound represented by the following formula (2) or (3) is introduced through said chemical compound having an end amino group. The object of the present invention is to provide a method of manufacturing a contact lens that prevents protein adsorption. n denotes a natural number 1-18.
    Type: Application
    Filed: May 18, 2005
    Publication date: February 14, 2008
    Inventors: Yukimitsu Suda, Kazuyuki Miyazawa, Kazuhiko Ishihara
  • Publication number: 20080007504
    Abstract: Disclosed herein is a liquid crystal display apparatus, including, a pixel array section, a first data line, a second data line, a writing unit, a voltage supply control unit, a data line short-circuiting unit, a reading out unit, and a testing unit.
    Type: Application
    Filed: June 12, 2007
    Publication date: January 10, 2008
    Inventors: Hideaki Kawaura, Kazutoshi Shimizume, Naoki Ando, Kazuyuki Miyazawa, Katsuhisa Hirano, Noriaki Horiguchi, Osamu Akimoto
  • Publication number: 20070242535
    Abstract: A semiconductor memory device formed on a semiconductor chip includes first memory arrays, a plurality of second memory arrays, a first voltage generator, and first bonding pads. The semiconductor chip is divided into first, second and third rectangle regions and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The first memory arrays are formed in the first rectangle region. The second memory arrays are formed in the second rectangle region. The voltage generator and first bonding pads are arranged in the third rectangle region. The first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the second memory arrays.
    Type: Application
    Filed: March 7, 2007
    Publication date: October 18, 2007
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20070241054
    Abstract: The present invention is affinity particles that are characterized by having phosphorylcholine groups represented by the following formula (1) covalently bonded onto the surface of organic particles and also by having ligands having specific affinity with a certain target substance covalently bonded or adsorbed onto the surface of organic particles. The object of the present invention is to provide an affinity separation method that uses affinity particles utilizing organic particles and is capable of separating the target substance easily and with high accuracy.
    Type: Application
    Filed: May 18, 2005
    Publication date: October 18, 2007
    Applicant: SHISEIDO COMPANY, LTD.
    Inventors: Kazuyuki Miyazawa, Katsuyuki Maeno
  • Patent number: 7257026
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: August 14, 2007
    Assignee: Elpida Memory, Inc.
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Publication number: 20070181503
    Abstract: The present invention is affinity particles that are characterized by having phosphorylcholine groups represented by the following formula (1) covalently bonded onto the surface of inorganic powder and also by having ligands having specific affinity with a certain target substance covalently bonded or adsorbed onto the surface of inorganic powder. The object of the present invention is to provide an affinity separation method that uses affinity particles utilizing inexpensive inorganic particles and is capable of separating the target substance easily and with high accuracy.
    Type: Application
    Filed: May 18, 2005
    Publication date: August 9, 2007
    Inventors: Katsuyuki Maeno, Kazuyuki Miyazawa, Akira Ishikubo, Kazuhiko Ishihara
  • Patent number: 7203101
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: April 10, 2007
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20070025598
    Abstract: An iris authentication apparatus includes an iris area extraction unit, registration pattern generating unit, collation pattern generating unit, and collation unit. The iris area extraction unit extracts iris areas from a sensed registration eyeball image and a sensed collation eyeball image. When the iris area extraction unit extracts an iris area from the registration eyeball image, the registration pattern generating unit generates a registration iris pattern image by performing polar coordinate transformation of an image in the extracted iris area. When the iris area extraction unit extracts an iris area from the collation eyeball image, the collation pattern generating unit generates a collation iris pattern image by performing polar coordinate transformation of an image in the extracted iris area.
    Type: Application
    Filed: July 28, 2006
    Publication date: February 1, 2007
    Inventors: Koji Kobayashi, Atsushi Katsumata, Hiroshi Nakajima, Kazuyuki Miyazawa, Koichi Ito, Takafumi Aoki
  • Publication number: 20060284646
    Abstract: A defective pixel examination method includes the steps of applying different voltages to a capacitive element of a first pixel section and a capacitive element of a second pixel section among the plurality of pixel sections; turning on a switch provided between an input electrode of a pixel transistor in the first pixel section and an input electrode of a pixel transistor in the second pixel section and short-circuiting the input electrode of the first pixel transistor and the input electrode of the second pixel transistor; reading a voltage of the capacitive element of the first pixel section and a voltage of the capacitive element of the second pixel section; and detecting defects of a pixel section on the basis of the result of the comparison between the voltage of the capacitive element of the first pixel section and the voltage of the capacitive element of the second pixel section.
    Type: Application
    Filed: June 5, 2006
    Publication date: December 21, 2006
    Applicant: Sony Corporation
    Inventors: Kazutoshi Shimizume, Kazuyuki Miyazawa, Shinichi Koga
  • Publication number: 20060221685
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Application
    Filed: May 5, 2006
    Publication date: October 5, 2006
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Patent number: 7079416
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 18, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Publication number: 20060120125
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Application
    Filed: January 12, 2006
    Publication date: June 8, 2006
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20060060533
    Abstract: A method for surface modification of a material by means of introducing the phosphorylcholine group represented by the following formula (1-1) onto the surface of the material by treating a material having amino groups with a chemical compound containing an aldehyde derivative obtained by the oxidative ring-opening reaction of glycerophosphorylcholine. The method of the present invention provides various materials such as medical materials having superior biocompatibility and hydrophilicity.
    Type: Application
    Filed: November 20, 2003
    Publication date: March 23, 2006
    Inventors: Kazuyuki Miyazawa, Taketoshi Kanda, Yousuke Toujo, Aya Ohkubo, Osamu Shirota, Kenichi Sukuma, Masayoshi Wada