Patents by Inventor Kazuyuki Miyazawa

Kazuyuki Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7016236
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: March 21, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Patent number: 6992343
    Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 31, 2006
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
  • Publication number: 20060020098
    Abstract: A polysiloxane having a phosphorylcholine group represented by the following general formula (1). To develop a method to obtain a polysiloxane having a phosphorylcholine group with ease and great versatility and provide a polysiloxane having a phosphorylcholine group in order to obtain a polysiloxane that has a wide range of application as a biocompatible material and a cosmetic material.
    Type: Application
    Filed: November 20, 2003
    Publication date: January 26, 2006
    Inventors: Kazuyuki Miyazawa, Takashi Oka
  • Publication number: 20050222405
    Abstract: The present invention is a method for manufacturing a phosphorylcholine group-containing polysaccharide wherein the aldehyde derivative-containing compound obtained by the oxidative ring-opening reaction of glycerophosphorylcholine is added to a polysaccharide containing amino groups as well as a new polysaccharide having phosphorylcholine groups obtained from this manufacturing method. The object of the present invention is to provide a phosphorylcholine group-containing polysaccharide that is superior in biocompatibility and moisture retention, and is useful as a polymer material for medical use, as well as a simple method of manufacturing it. The polysaccharide of the present invention is utilized, for example, in artificial organs, biomembranes, coating agents for medical tools, drug delivery, and in cosmetics.
    Type: Application
    Filed: April 8, 2003
    Publication date: October 6, 2005
    Inventors: Kazuyuki Miyazawa, Toshio Yanaki, Francoise Winnik
  • Publication number: 20050179058
    Abstract: A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
    Type: Application
    Filed: April 8, 2005
    Publication date: August 18, 2005
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Patent number: 6906971
    Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: June 14, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Nakamura, Kazuyuki Miyazawa, Hidetoshi Iwai
  • Publication number: 20050122803
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Application
    Filed: January 25, 2005
    Publication date: June 9, 2005
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Patent number: 6898130
    Abstract: A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. This structure in which the peripheral circuits are arranged at the center portion of the chip permits the longest signal transition paths to be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: May 24, 2005
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20050056876
    Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6 F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2 F and smaller than 4 F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
    Type: Application
    Filed: October 29, 2004
    Publication date: March 17, 2005
    Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
  • Publication number: 20050013167
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Application
    Filed: August 18, 2004
    Publication date: January 20, 2005
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Patent number: 6828612
    Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell·two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: December 7, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Elpida Memory, Inc.
    Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
  • Publication number: 20040240259
    Abstract: Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
    Type: Application
    Filed: October 14, 2003
    Publication date: December 2, 2004
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20040184330
    Abstract: A semiconductor IC device includes, in a substrate, a P-type well region having a dynamic memory array section and applied with a reduced back bias voltage suitable for refreshing. Also included is a P-well region where N-channel MOSFETs of a peripheral circuit are formed. This P-well region is applied with a back bias voltage of an absolute value smaller than that applied to the P-type well of the memory array section. A P-type well section, where there are formed N-channel MOSFETs of an input circuit or an output circuit connected with external terminals, is applied with a back bias voltage of an absolute value large enough to provide a measure of protection against undershoot, while the refresh characteristics are improved by reducing the leakage current between the source/drain region connected with a capacitor and the P-type well, to thereby raise the operation speed of the peripheral circuit.
    Type: Application
    Filed: January 30, 2004
    Publication date: September 23, 2004
    Inventors: Masayuki Nakamura, Kazuyuki Miyazawa, Hidetoshi Iwai
  • Patent number: 6788572
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: September 7, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Patent number: 6657901
    Abstract: A semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. A benefit of this structure in which the peripheral circuits are arranged at the center portion of the chip, is that the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 2, 2003
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Kazuhiko Kajigaya, Kazuyuki Miyazawa, Manabu Tsunozaki, Kazuyoshi Oshima, Takashi Yamazaki, Yuji Sakai, Jiro Sawada, Yasunori Yamaguchi, Tetsurou Matsumoto, Shinji Udo, Hiroshi Yoshioka, Hirokazu Saito, Mitsuhiro Takano, Makoto Morino, Sinichi Miyatake, Eiji Miyamoto, Yasuhiro Kasama, Akira Endo, Ryoichi Hori, Jun Etoh, Masashi Horiguchi, Shinichi Ikenaga, Atsushi Kumata
  • Publication number: 20030214850
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z., and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Application
    Filed: June 6, 2003
    Publication date: November 20, 2003
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Publication number: 20030173593
    Abstract: A semiconductor memory device is provided which can achieve the high integration, ultra-high speed operation, and significant reduction of power consumption during the information holding time, by reducing the increase in the area of a memory cell and obtaining a period of the ultra-high speed readout time and ensuring a long refresh period at the time of the self refresh. A DRAM employing a one-intersection cell•two cells/bit method has a twin cell structure employing a one-intersection 6F2 cell, the structure in which: memory cells are arranged at positions corresponding to all of the intersections between a bit-line pair and a word line; and when a half pitch of the word line is defined as F, a pitch of each bit line of the bit-line pair is larger than 2F and smaller than 4F. Further, an active region in the silicon substrate, on which a source, channel and drain of the transistor of each memory cell are formed, is obliquely formed relative to the direction of the bit-line pair.
    Type: Application
    Filed: March 17, 2003
    Publication date: September 18, 2003
    Inventors: Shinichi Miyatake, Kazuhiko Kajigaya, Kazuyuki Miyazawa, Tomonori Sekiguchi, Riichiro Takemura, Takeshi Sakata
  • Patent number: 6590808
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: July 8, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Publication number: 20030117843
    Abstract: In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect the reading and erasing. Concretely, the memory array is so constituted that it can be accessed by three-dimensional address of X, Y and Z, and multi-bit data in the memory cell is discriminated by the Z-address.
    Type: Application
    Filed: November 6, 2002
    Publication date: June 26, 2003
    Inventors: Naoki Yamada, Hiroshi Sato, Tetsuya Tsujikawa, Kazuyuki Miyazawa
  • Publication number: 20030072805
    Abstract: The present invention provides a microgel having a mean particle size of 0.1-1,000 &mgr;m, the microgel being produced from a gel which is formed by use of a hydrophilic compound capable of forming a gel. An external composition containing the microgel provides an excellent sensation during use; i.e., the composition provides neither sticky sensation during use nor frictional sensation. Furthermore, even when a large amount of a pharmaceutical ingredient, such as a whitening ingredient, or a salt is incorporated into the composition, the viscosity of the composition is not lowered, and the composition exhibits excellent viscosity increasing property. In addition, the composition exhibits long-term stability, without inviting separation of water.
    Type: Application
    Filed: November 6, 2001
    Publication date: April 17, 2003
    Inventors: Kazuyuki Miyazawa, Isamu Kaneda, Toshio Yanaki, Tadashi Nakamura, Masatoshi Ochiai, Tomoyuki Kawasoe