Patents by Inventor Kazuyuki Sugahara

Kazuyuki Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11158511
    Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 26, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazuyuki Sugahara, Hiroaki Okabe, Motoru Yoshida
  • Patent number: 11117365
    Abstract: A printing device includes a controller configured or programmed to acquire, based on a width of a coating material that has been measured, at least one of a start position, an end position, or an amount of movement of a coating material scooping unit in coating material scooping operation.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: September 14, 2021
    Assignee: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Takeshi Fujimoto, Katsumi Totani, Takeshi Miwa, Kazuyuki Sugahara
  • Publication number: 20210237425
    Abstract: A printing device includes a controller configured or programmed to acquire, based on a width of a coating material that has been measured, at least one of a start position, an end position, or an amount of movement of a coating material scooping unit in coating material scooping operation.
    Type: Application
    Filed: June 5, 2018
    Publication date: August 5, 2021
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Takeshi FUJIMOTO, Katsumi TOTANI, Takeshi MIWA, Kazuyuki SUGAHARA
  • Patent number: 11063122
    Abstract: In a termination region of a SiC-MOSFET, suppressing operation of a p-n diode between a well and a drift layer sometimes decreases reliability during high-speed switching. In a termination region of a SiC-MOSFET with a built-in SBD are provided second well region having an impurity concentration lower than the impurity concentration in a well region in an active region, and a high-concentration region that is formed on a surface layer of the second well region, has an impurity concentration higher than the impurity concentration in the well region in the active region, and is ohmic-connected to a source electrode.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: July 13, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yusuke Yamashiro, Kazuyuki Sugahara, Hiroshi Watanabe, Kohei Ebihara
  • Publication number: 20210122152
    Abstract: A printing device includes a coating material scooping unit configured to scoop a coating material on a mask, and a controller configured or programmed to determine whether or not the coating material scooping unit performs collecting operation to collect the coating material on the mask when the mask is replaced.
    Type: Application
    Filed: June 5, 2018
    Publication date: April 29, 2021
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Takeshi FUJIMOTO, Kazuyuki SUGAHARA, Takeshi MIWA, Jinok PARK
  • Patent number: 10707146
    Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: July 7, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Motoru Yoshida, Yoshiyuki Suehiro, Kazuyuki Sugahara, Yosuke Nakanishi, Yoshinori Yokoyama, Shinnosuke Soda, Komei Hayashi
  • Publication number: 20200127098
    Abstract: In a termination region of a SiC-MOSFET, suppressing operation of a p-n diode between a well and a drift layer sometimes decreases reliability during high-speed switching. In a termination region of a SiC-MOSFET with a built-in SBD are provided second well region having an impurity concentration lower than the impurity concentration in a well region in an active region, and a high-concentration region that is formed on a surface layer of the outer periphery second well region, has an impurity concentration higher than the impurity concentration in the well region in the active region, and is ohmic-connected to a source electrode.
    Type: Application
    Filed: October 24, 2017
    Publication date: April 23, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Yusuke YAMASHIRO, Kazuyuki SUGAHARA, Hiroshi WATANABE, Kohei EBIHARA
  • Patent number: 10276502
    Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.
    Type: Grant
    Filed: November 27, 2015
    Date of Patent: April 30, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Motoru Yoshida, Hiroaki Okabe, Kazuyuki Sugahara
  • Publication number: 20190122955
    Abstract: Provided is a semiconductor device having high heat conductivity and high productivity. A semiconductor device includes an insulating substrate, a semiconductor element, a die-bond material, a joining material, and a cooler. The insulating substrate has an insulating ceramic, a first conductive plates disposed on one surface of the insulating ceramic, and a second conductive plate disposed on another surface of the insulating ceramic. The semiconductor element is disposed on the first conductive plate through the die-bond material. The die-bond material contains sintered metal. The semiconductor element has a bending strength degree of 700 MPa or more, and has a thickness of 0.05 mm or more and 0.1 mm or less. The cooler is joined to the second conductive plate through the joining material.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 25, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Motoru YOSHIDA, Yoshiyuki SUEHIRO, Kazuyuki SUGAHARA, Yosuke NAKANISHI, Yoshinori YOKOYAMA, Shinnosuke SODA, Komei HAYASHI
  • Publication number: 20190057873
    Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.
    Type: Application
    Filed: February 2, 2017
    Publication date: February 21, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuyuki SUGAHARA, Hiroaki OKABE, Motoru YOSHIDA
  • Publication number: 20180040563
    Abstract: A method for manufacturing a semiconductor device includes: a process of forming a Cu wiring electrode by a plating method above a semiconductor element using a wide bandgap semiconductor as a base material; a reducing process of reducing the Cu wiring electrode under a NH3 atmosphere; a heating process of heating the Cu wiring electrode at the same time as the reducing process; a process of forming a diffusion prevention film covering the Cu wiring electrode after the heating process; and a sealing process of covering the diffusion prevention film with an organic resin film.
    Type: Application
    Filed: November 27, 2015
    Publication date: February 8, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Motoru YOSHIDA, Hiroaki OKABE, Kazuyuki SUGAHARA
  • Patent number: 9842738
    Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: December 12, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Yosuke Nakanishi, Hiroaki Okabe, Motoru Yoshida, Kazuyuki Sugahara, Takaaki Tominaga
  • Patent number: 9721915
    Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.
    Type: Grant
    Filed: February 16, 2015
    Date of Patent: August 1, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Motoru Yoshida, Kazuyo Endo, Jun Fujita, Hiroaki Okabe, Kazuyuki Sugahara
  • Publication number: 20170032968
    Abstract: A method of manufacturing a silicon carbide semiconductor device is provided. The method suppresses the increase in the number of manufacturing steps and is capable of suppressing the degradation of ohmic characteristics of an alloy layer with respect to a semiconductor substrate. The method includes a step of forming a metal layer made of a first metal on a semiconductor substrate made of silicon carbide; a step of forming a metal nitride film obtained by nitriding a second metal on the metal layer; a step of directing a laser light through the metal nitride film to form a layer of an alloy of silicon carbide in the semiconductor substrate and the first metal in the metal layer; and a step of forming an electrode on the metal nitride film.
    Type: Application
    Filed: April 9, 2014
    Publication date: February 2, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yosuke NAKANISHI, Hiroaki OKABE, Motoru YOSHIDA, Kazuyuki SUGAHARA, Takaaki TOMINAGA
  • Publication number: 20160358874
    Abstract: A semiconductor device capable of inhibiting oxidation of a Cu wiring even in a high temperature operation. The semiconductor device includes a semiconductor substrate having a main surface, a Cu electrode which is selectively formed on a side of the main surface of the semiconductor substrate, an antioxidant film formed on an upper surface of the Cu electrode except an end portion thereof, an organic resin film which is formed on the main surface of the semiconductor substrate and covers a side surface of the Cu electrode and the end portion of the upper surface thereof, and a diffusion prevention film formed between the organic resin film and the main surface of the semiconductor substrate and between the organic resin film and the side surface and the end portion of the upper surface of the Cu electrode, being in contact therewith.
    Type: Application
    Filed: February 16, 2015
    Publication date: December 8, 2016
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Motoru YOSHIDA, Kazuyo ENDO, Jun FUJITA, Hiroaki OKABE, Kazuyuki SUGAHARA
  • Patent number: 9120631
    Abstract: A board working system includes a board working apparatus working on a board and a board conveying apparatus including a first board conveying portion, connected to the board working apparatus. The board conveying apparatus is provided with a shutter device closing such that the maximum interval of an opening gap leading from the first board conveying portion to the board working apparatus is not more than a prescribed value when setup for the first board conveying portion is performed.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: September 1, 2015
    Assignee: Yamaha Hatsudoki Kabushiki Kaisha
    Inventors: Kazuyuki Sugahara, Toshihiko Ohata
  • Publication number: 20140131166
    Abstract: A board working system includes a board working apparatus working on a board and a board conveying apparatus including a first board conveying portion, connected to the board working apparatus. The board conveying apparatus is provided with a shutter device closing such that the maximum interval of an opening gap leading from the first board conveying portion to the board working apparatus is not more than a prescribed value when setup for the first board conveying portion is performed.
    Type: Application
    Filed: November 14, 2013
    Publication date: May 15, 2014
    Applicant: YAMAHA HATSUDOKI KABUSHIKI KAISHA
    Inventors: Kazuyuki SUGAHARA, Toshihiko OHATA
  • Patent number: 8685674
    Abstract: A vector of the present invention has DNA encoding a protein or a product having the same effect as the protein, the protein containing an amino acid sequence from amino acid numbers 47 to 802 in SEQ. ID. NO:2. Expression of the DNA gives human chondroitin synthase. By using human chondroitin synthase, it is possible to produce a saccharide chain having a repeating disaccharide unit of chondroitin. The DNA or part thereof may be used as a probe for hybridization for the human chondroitin synthase.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: April 1, 2014
    Assignee: Glytech, Inc.
    Inventors: Kazuyuki Sugahara, Hiroshi Kitagawa
  • Patent number: 8481290
    Abstract: An antibody specific for a chondroitin sulphate epitope is described, as is a hybridoma cell line which produces such an antibody. The antibody is useful in the diagnosis and treatment of connective tissue diseases, such as arthritis and sarcomas. Test kits and pharmaceutical compositions are also described.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: July 9, 2013
    Assignees: The National Research Council of Thailand, The Thailand Research Fund, Chiang Mai University of Thailand
    Inventors: Prachya Kongtawelert, Tim Hardingham, Siriwan Ong-Chai, Kazuyuki Sugahara, Peraphan Pothacharoen, Nattachai Tiengburanathum
  • Publication number: 20130034878
    Abstract: A vector of the present invention has DNA encoding a protein or a product having the same effect as the protein, the protein containing an amino acid sequence from amino acid numbers 47 to 802 in SEQ. ID. NO:2. Expression of the DNA gives human chondroitin synthase. By using human chondroitin synthase, it is possible to produce a saccharide chain having a repeating disaccharide unit of chondroitin. The DNA or part thereof may be used as a probe for hybridization for the human chondroitin synthase.
    Type: Application
    Filed: October 9, 2012
    Publication date: February 7, 2013
    Inventors: Kazuyuki Sugahara, Hiroshi Kitagawa