Abstract: The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer includes a plurality of domains with an equal area, the plurality of domains include at least two types of domains, the at least two types of domains are arranged in a mosaic shape; a plurality of gate lines extending along a row direction and a plurality of data lines extending along a column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.

Abstract: According to a liquid crystal display panel and a display device in the present disclosure, since at least one of a first polarizer and a second polarizer has a light scattering structure, polarized light of corresponding colors transmitted by sub-pixel units with different colors in a liquid crystal display structure can be uniformly diffused by the light scattering structure. That is to say, the light scattering structure plays a role for uniformly mixing the polarized light of different colors. Therefore, the rainbow pattern phenomenon is effectively improved or even eliminated, and the display quality is improved.

Abstract: The present disclosure provides a liquid crystal display panel and a liquid crystal display device. The liquid crystal display panel includes a plurality of sub-pixels defined by a light shielding matrix, and an array substrate and an opposing substrate arranged to be spaced apart from each other. The opposing substrate includes a first substrate and a plurality of spacers, wherein the spacers are on a side of the first substrate close to the array substrate and being within a light shielding area of the light shielding matrix. The array substrate includes a second substrate and a plurality of protrusion structures, wherein the protrusion structures are on a side of the second substrate close to the opposing substrate, and being within the light shielding area of the light shielding matrix.

Abstract: A system and a method for power conversion. The system includes a rectifier; an inverter; a DC-link capacitor coupled between the rectifier and the inverter; and a controller. The controller is configured to obtain a current value at an output of the inverter and a voltage value across the DC-link capacitor, determine an average component and a fluctuating component of an output voltage of the inverter based on the obtained current value and the voltage value, and determine a current reference for controlling the rectifier based on the average component and the fluctuating component of the output voltage.

Abstract: The present disclosure provides an array substrate, a dimming liquid crystal panel and a display panel. The array substrate includes: a first transparent electrode layer with a plurality of slit structures, wherein the first transparent electrode layer comprises a plurality of domains, the plurality of domains comprise at least two types of domains, each of the plurality of domains is adjacent to different types of domains along both a row direction and a column direction; and a plurality of gate lines extending along the row direction and a plurality of data lines extending along the column direction, the plurality of gate lines and the plurality of data lines crossing to define a plurality of dimming regions arranged in an array.

Abstract: A display device, a gate drive circuit, a shift register and a control method are disclosed. The shift register includes a first shift register unit and a second shift register unit, the first shift register unit is configured to write a first control signal to the first node, and write a first clock signal to the first signal output terminal under control of a voltage of the first node; the second shift register unit is configured to write a second clock signal to the second signal output terminal under control of the voltage of the first node; during time of a frame, the first clock signal and a first input signal provided by a first signal input terminal are pulse signals, and the second clock signal is a DC signal.

Abstract: An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

Abstract: A method for improving a halo is applied to a display panel. The display panel includes a dimming sub-panel and a display sub-panel that are superposed. The dimming sub-panel includes a plurality of first pixels, the display sub-panel includes a plurality of second pixels, and each first pixel corresponds to at least two second pixels. The method for improving the halo includes: as for the first pixel: acquiring a second brightness datum of each of the at least two second pixels corresponding to the first pixel; calculating a target brightness datum of the first pixel according to second brightness data of the at least two second pixels; determining a first gray-scale datum of the first pixel according to the target brightness datum.

Abstract: There is provided a display substrate, including gate lines and data lines, which define pixel units, each pixel unit includes a pixel electrode, at least some pixel units are provided with a conductive bridge line in a same layer as the pixel electrode; in the pixel unit with the conductive bridge line, a first hollow structure is on a first side of a first or second end part of the pixel electrode, an end of the conductive bridge line is in the first hollow structure, a second hollow structure is on a second side of the first end part, an absolute value of a difference between parasitic capacitances respectively formed between the pixel electrode and the data lines on two sides of the pixel electrode and closest thereto is less than or equal to a preset capacitance difference value. A display panel and a display device are further provided.

Abstract: A display device and a manufacturing method thereof, an electronic device, and a light control panel are provided. The display device includes a light control panel and a display liquid crystal panel. The display liquid crystal panel is on a light-emitting side of the light control panel; the light control panel includes a light control region, and the light control region is configured to provide adjusted backlight to the display liquid crystal panel; the display liquid crystal panel includes a display region, and the display region is configured to receive the adjusted backlight to perform display; and a distance between two opposite edges of the light control region in at least one direction is greater than a distance between two opposite edges of the display region in the at least one direction.

Abstract: The present disclosure generally relates to display technologies. An array substrate includes a plurality of repeating units arranged in a first direction, each repeating unit including a plurality of connection areas and a plurality of shared testing areas arranged in an alternating manner in a row along the first direction. Each of the plurality of shared testing areas is between two adjacent connection areas and coupled to each of the two adjacent connection areas, and each of the plurality of shared testing areas includes a plurality of testing pads, a first portion of the plurality of testing pads being coupled to one of the two adjacent connection areas, a second portion of the plurality of testing pads being coupled to the other one of the two adjacent connection areas.

Abstract: Provided is an array substrate. The array substrate includes at least one pad group disposed in a peripheral region of a base substrate, wherein the at least one pad group includes a sector pad group in which the pads are distributed in a sector shape. Therefore, the bonding yield between the array substrate and the circuit board is increased.

Abstract: Disclose are a display substrate, a liquid crystal display panel and a display device. The display substrate is provided with a display region. The display substrate includes: a base substrate, and a black matrix arranged on a side of the base substrate. The black matrix includes: a first region corresponding to the display region, and a plurality of frame regions arranged on a periphery of the first region. At least one rectilinear first slit and at least one rectilinear second slit intersecting with the at least one rectilinear first slit are arranged in the at least one of the frame regions, and an extending direction of the at least one rectilinear first slit is same as an extending direction of the at least one of the frame regions.

Abstract: A display device, a gate drive circuit, a shift register and a control method are disclosed. A first shift register unit of the shift register is configured to write a first control signal to a first node under control of a first input signal, write a first clock signal to a first signal output terminal; a second shift register unit of the shift register is configured to write a second control signal to the first node under control of a second input signal, write a second clock signal to a second signal output terminal; during the first frame, the first clock signal and the first input signal are pulse signals, the second clock signal and the second input signal are DC signals; during the second frame, the first clock signal and the first input signal are DC signals, the second clock signal and the second input signal are pulse signals.

Abstract: An array substrate having a display area, a peripheral area, and a bonding area inside the peripheral area is provided. The array substrate includes a bonding pad in the bonding area, the bonding pad configured to be connected to a peripheral circuit through a bonding connector, a test signal line including a first portion and a second portion. The first portion is in the peripheral area and substantially surrounds the display area. The first portion is electrically connected to the bonding pad. The first portion is completely inside the array substrate and has no exposed terminal. The second portion is in the bonding area. A first terminal of the second portion is electrically connected to the bonding pad. A second terminal of the second portion has an end along an edge of the array substrate in the bonding area.

Abstract: An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes sub-pixel units, and each sub-pixel unit includes a light emitting region and a non-light emitting region; each sub-pixel unit includes a light emitting element, the light emitting element includes a light emitting layer and a first electrode, and at least a part of the first electrode is in the light emitting region. A plurality of first wires are configured to supply a power signal to the light emitting element and include a first sub-wire; the first sub-wire includes a plurality of portions, adjacent two of the plurality of portions are spaced apart from each other by an opening in the light emitting region; at least a part of an orthographic projection of the opening on the array substrate does not overlap with an orthographic projection of the first electrode on the array substrate.

Abstract: A transformer can include at least one magnetic core; a substrate having a planar winding inside; and where the substrate is stacked with at least one of the magnetic cores. A package module can include the transformer and a package backplane a package backplane that encapsulates a wafer; and where the package backplane is stacked with the transformer, and an upper surface of the package backplane is in contact with the magnetic core of the transformer.

Abstract: The present disclosure provides a circuit control method and a control device, a display module and a display device. The circuit control device is used for acquiring an indication signal for indicating whether a user performs touch operation on the touch panel or not; the current is provided for the driving circuit according to the indication signal, a first current is provided for the driving circuit under the condition that a user does not carry out touch operation on the touch panel, a second current is provided for the driving circuit under the condition that the user carries out touch operation on the touch panel, and the second current is larger than the first current.

Abstract: The preset disclosure provides a display control method, a timing controller IC and a display device. The method includes: acquiring a preset grayscale voltage of a target pixel unit and a backlight brightness of a backlight region corresponding to the target pixel unit, in a current output display frame; outputting a first grayscale voltage to the target pixel unit if the backlight brightness of the corresponding backlight region is less than or equal to a first preset brightness value; outputting a second grayscale voltage to the target pixel unit if the backlight brightness of the corresponding backlight region is greater than the first preset brightness value; wherein the second grayscale voltage is greater than the first grayscale voltage, and both the second grayscale voltage and the first grayscale voltage are greater than the preset grayscale voltage.

Abstract: A common voltage calibration circuit and a driving method thereof, a circuit board and a display device are provided. The common voltage calibration circuit includes a difference circuit, a compensation circuit and a summing circuit; the difference circuit is configured to perform a difference processing on a common voltage provided by the common voltage input terminal and a feedback common voltage provided by the common voltage feedback terminal to output a difference value signal; the compensation circuit is configured to receive the difference value signal and compensate the common voltage based on the difference value signal; and the summing circuit is configured to superimpose at least two compensation signals output by the compensation circuit and output through the common voltage output terminal.