Patents by Inventor Ke Yan Tean
Ke Yan Tean has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240395646Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: August 1, 2024Publication date: November 28, 2024Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Publication number: 20240387305Abstract: A semiconductor package includes: a die pad having opposing first and second sides and lateral sides connecting the first and second sides; at least one semiconductor die arranged over the first side; an encapsulation including a first dielectric material and encapsulating the semiconductor die, the second side of the die pad being at least partially exposed from the encapsulation; and a contiguous isolation structure including a second dielectric material different from the first dielectric material and covering the second side of the die pad. The encapsulation includes at least one first trench arranged along at least a part of a contour of the second side of the die pad. The second side of the die pad includes at least one second trench arranged along at least a part of the contour of the second side of the die pad. The trenches are filled by the contiguous isolation structure.Type: ApplicationFiled: April 26, 2024Publication date: November 21, 2024Inventors: Meng How Chong, Muhammad Safie Rosli, Michael Reyes Godoy, Ke Yan Tean
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Patent number: 12094793Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: GrantFiled: October 16, 2023Date of Patent: September 17, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
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Patent number: 12057376Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.Type: GrantFiled: November 2, 2020Date of Patent: August 6, 2024Assignee: Infineon Technologies AGInventors: Azlina Kassim, Thai Kee Gan, Mark Pavier, Ke Yan Tean, Mohd Hasrul Zulkifli
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Publication number: 20240234256Abstract: A package is disclosed. In one example, the package comprises a carrier having a front side and a back side, an electronic component mounted on the front side of the carrier, and an encapsulant at least partially encapsulating the electronic component and partially encapsulating the carrier so that the back side is at least partially exposed with respect to the encapsulant. The back side of the carrier has at least one vacuum suction enhancing indentation for enhancing vacuum suction of the carrier during encapsulation.Type: ApplicationFiled: November 24, 2023Publication date: July 11, 2024Applicant: Infineon Technologies AGInventors: Nor Samsiah MARZUKI, Arivindran NAVARETNASINGGAM, Narayanan CHELLIAH, Ke Yan TEAN, Rolando Pontillas ENVERGA
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Publication number: 20240087992Abstract: A chip package is provided. The chip package includes a first chip, a second chip, an electrically conductive structure to which the first chip and the second chip are mounted, at least one contact terminal for electrically contacting the first chip and/or the second chip, and encapsulation material at least partially encapsulating the first chip, the second chip, and the electrically conductive structure. The encapsulation material forms a chip package body from which the at least one contact terminal protrudes. At least a portion of the electrically conductive structure forms a portion of an outer surface of the chip package body.Type: ApplicationFiled: August 22, 2023Publication date: March 14, 2024Inventors: Ke Yan Tean, Edmund Sales Cabatbat, Kean Ming Koe
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Publication number: 20240038612Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 16, 2023Publication date: February 1, 2024Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Patent number: 11876028Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: GrantFiled: October 15, 2021Date of Patent: January 16, 2024Assignee: Infineon Technologies AGInventors: Edward Fuergut, Chii Shang Hong, Teck Sim Lee, Bernd Schmoelzer, Ke Yan Tean, Lee Shuang Wang
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Patent number: 11804424Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: GrantFiled: December 1, 2020Date of Patent: October 31, 2023Assignee: Infineon Technologies Austria AGInventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Patent number: 11652078Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.Type: GrantFiled: April 20, 2021Date of Patent: May 16, 2023Assignee: Infineon Technologies AGInventors: Edmund Sales Cabatbat, Thai Kee Gan, Kean Ming Koe, Ke Yan Tean
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Patent number: 11621204Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.Type: GrantFiled: February 17, 2021Date of Patent: April 4, 2023Assignee: Infineon Technologies AGInventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
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Patent number: 11600547Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.Type: GrantFiled: December 2, 2019Date of Patent: March 7, 2023Assignee: Infineon Technologies Austria AGInventors: Jo Ean Joanna Chye, Teck Sim Lee, Ke Yan Tean, Wei-Shan Wang
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Publication number: 20220336401Abstract: A semiconductor package includes a die pad, a semiconductor die mounted on the die pad and comprising a first terminal facing away from the die pad and a second terminal facing and electrically connected to the die pad, an interconnect clip electrically connected to the first terminal, an encapsulant body of electrically insulating material that encapsulates the semiconductor die and the interconnect clip, and a first opening in the encapsulant body that exposes a surface of the interconnect clip, the encapsulant body comprises a lower surface, an upper surface opposite from the lower surface, and a first outer edge side extending between the lower surface and the upper surface, and the first opening is laterally offset from the first outer edge side.Type: ApplicationFiled: April 20, 2021Publication date: October 20, 2022Inventors: Edmund Sales Cabatbat, Thai Kee Gan, Kean Ming Koe, Ke Yan Tean
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Publication number: 20220262693Abstract: A semiconductor module includes: a dual-gauge leadframe having thicker and thinner parts, part of the thinner part forming a high voltage lead; a semiconductor die attached to the thicker part; and a molding compound (MC) encapsulating the die. The thicker leadframe part is disposed at a bottom side of the MC. A side face of the MC has a stepped region between the high voltage lead and thicker leadframe part. A first generally vertical part of the stepped region extends from the high voltage lead to the generally horizontal part, a generally horizontal part of the stepped region extends to the second generally vertical part, and a second generally vertical part of the stepped region extends to the bottom side of the MC. A linear dimension of the generally horizontal part as measured from the first generally vertical part to the second generally vertical part is at least 4.5 mm.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Inventors: Oliver Markus Kreiter, Ludwig Busch, Angel Enverga, Mei Fen Hiew, Tian See Hoe, Elvis Keli, Kean Ming Koe, Sanjay Kumar Murugan, Michael Niendorf, Ivan Nikitin, Bernhard Stiller, Thomas Stoek, Ke Yan Tean
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Publication number: 20220157682Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.Type: ApplicationFiled: October 15, 2021Publication date: May 19, 2022Applicant: Infineon Technologies AGInventors: Edward FUERGUT, Chii Shang HONG, Teck Sim LEE, Bernd SCHMOELZER, Ke Yan TEAN, Lee Shuang WANG
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Publication number: 20220139811Abstract: An interconnect clip includes a die attach pad that comp includes rises a die attach surface at an inner side of the interconnect clip, a heat dissipation pad that includes a heat dissipation surface at an outer side of the interconnect clip, and a lead contact pad that includes a lead contact surface at an inner side of the interconnect clip or at an outer side of the interconnect clip. The outer side of the interconnect clip in the lead contact pad faces and is spaced apart from the inner side of the interconnect clip in the heat dissipation pad, and the inner side of the interconnect clip in the lead contact pad faces and is spaced apart from the outer side of the interconnect clip in the die attach pad.Type: ApplicationFiled: November 2, 2020Publication date: May 5, 2022Inventors: Azlina Kassim, Thai Kee Gan, Mark Pavier, Ke Yan Tean, Mohd Hasrul Zulkifli
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Patent number: 11211353Abstract: A clip for a semiconductor package and a semiconductor having a clip is disclosed. In one example, the clip includes a first planar portion, a plurality of first pillars, and a plurality of first solder balls. Each first pillar of the plurality of first pillars is coupled to the first planar portion. Each first solder ball of the plurality of first solder balls is coupled to a corresponding first pillar of the plurality of first pillars.Type: GrantFiled: July 9, 2019Date of Patent: December 28, 2021Assignee: Infineon Technologies AGInventors: Mohd Kahar Bajuri, Abdul Rahman Mohamed, Siang Kuan Chua, Ke Yan Tean
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Patent number: 11069600Abstract: A semiconductor package includes a die pad having a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile, wherein an upper section of the die pad laterally overhangs past a lower section of the die pad, a semiconductor die mounted on the die attach surface and having a first electrical terminal on an upper surface of the semiconductor die, and a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.Type: GrantFiled: May 24, 2019Date of Patent: July 20, 2021Assignee: Infineon Technologies AGInventors: Ke Yan Tean, Thomas Bemmerl, Thai Kee Gan, Azlina Kassim
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Publication number: 20210175157Abstract: A semiconductor device includes a carrier, a first external contact, a second external contact, and a semiconductor die. The semiconductor die has a first main face, a second main face opposite to the first main face, a first contact pad disposed on the first main face, a second contact pad disposed on the second main face, a third contact pad disposed on the second main face, and a vertical transistor. The semiconductor die is disposed with the first main face on the carrier. A clip connects the second contact pad to the second external contact. A first bond wire is connected between the third contact pad and the first external contact. The first bond wire is disposed at least partially under the clip.Type: ApplicationFiled: December 1, 2020Publication date: June 10, 2021Inventors: Ralf Otremba, Chii Shang Hong, Jo Ean Joanna Chye, Teck Sim Lee, Hui Kin Lit, Ke Yan Tean, Lee Shuang Wang, Wei-Shan Wang
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Publication number: 20210166988Abstract: A semiconductor package includes a die pad having a die attach surface, a first laterally separated and vertically offset from the die pad, a semiconductor die mounted on the die attach surface and comprising a first terminal on an upper surface of the semiconductor die, an interconnect clip that is electrically connected to the first terminal and to the first lead, and a heat spreader mounted on top of the interconnect clip. The interconnect clip includes a first planar section that interfaces with the upper surface of the semiconductor die and extends past an outer edge side of the die pad. The heat spreader covers an area of the first planar section that is larger than an area of the semiconductor die. The heat spreader laterally extends past a first outer edge side of the die pad that faces the first lead.Type: ApplicationFiled: December 2, 2019Publication date: June 3, 2021Inventors: Jo Ean Joanna Chye, Teck Sim Lee, Ke Yan Tean, Wei-Shan Wang