Patents by Inventor Kei Murayama
Kei Murayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11817381Abstract: A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin formed from a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the encapsulation resin. The covering resin is disposed on the upper surface of the upper substrate and covers a side surface of the wiring layer.Type: GrantFiled: July 15, 2021Date of Patent: November 14, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Murayama, Mitsuhiro Aizawa, Amane Kaneko, Kiyoshi Oi
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Patent number: 11706877Abstract: A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.Type: GrantFiled: May 2, 2022Date of Patent: July 18, 2023Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Shota Miki, Koyuki Kawakami, Kiyoshi Oi, Kei Murayama, Mitsuhiro Aizawa
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Publication number: 20230207443Abstract: A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, one or more through holes extending through the upper substrate in a thickness-wise direction, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin covering the upper surface of the upper substrate and filling the through holes.Type: ApplicationFiled: December 20, 2022Publication date: June 29, 2023Inventor: Kei MURAYAMA
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Publication number: 20220361342Abstract: A composite wiring substrate includes a first wiring substrate including a first connection terminal, a second wiring substrate including a second connection terminal facing the first connection terminal, and a joint material joining the first connection terminal and the second connection terminal. The first outline of the first connection terminal is inside the second outline of the second connection terminal in a plan view. The joint material includes a first portion formed of an intermetallic alloy of copper and tin, and contacting each of the first connection terminal and the second connection terminal, and a second portion formed of an alloy of tin and bismuth, and including a portion between the first outline and the second outline in the plan view. The second portion contains the bismuth at a higher concentration than in the eutectic composition of a tin-bismuth alloy, and is separated from the second connection terminal.Type: ApplicationFiled: May 2, 2022Publication date: November 10, 2022Inventors: Shota MIKI, Koyuki KAWAKAMI, Kiyoshi OI, Kei MURAYAMA, Mitsuhiro AIZAWA
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Publication number: 20220028774Abstract: A semiconductor device includes a lower substrate, a semiconductor element mounted on an upper surface of the lower substrate, an upper substrate disposed on an upper surface of the semiconductor element, an encapsulation resin disposed between the lower substrate and the upper substrate and encapsulating the semiconductor element, a wiring layer disposed on an upper surface of the upper substrate, and a covering resin formed from a material having a coefficient of thermal expansion similar to a coefficient of thermal expansion of the encapsulation resin. The covering resin is disposed on the upper surface of the upper substrate and covers a side surface of the wiring layer.Type: ApplicationFiled: July 15, 2021Publication date: January 27, 2022Inventors: Kei MURAYAMA, Mitsuhiro AIZAWA, Amane KANEKO, Kiyoshi OI
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Patent number: 10959328Abstract: A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.Type: GrantFiled: June 29, 2020Date of Patent: March 23, 2021Inventors: Naoki Kobayashi, Kei Murayama, Mitsuhiro Aizawa, Shota Miki
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Publication number: 20210007220Abstract: A wiring substrate includes: a wiring structure that includes a wiring layer and an insulating layer laminated; a plurality of first posts that are formed along a periphery of a predetermined area on a surface of the wiring structure, and that protrude out from the surface of the wiring structure; and a second post that is connected to the wiring layer at a position surrounded by the first posts, and that protrudes out from the surface of the wiring structure. The first posts are formed such that a post arranged at a central portion of a side constituting the periphery of the predetermined area is lower in height from the surface of the wiring structure than posts arranged at both ends of the side.Type: ApplicationFiled: June 29, 2020Publication date: January 7, 2021Inventors: Naoki Kobayashi, Kei Murayama, Mitsuhiro Aizawa, Shota Miki
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Patent number: 10784226Abstract: A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer.Type: GrantFiled: May 30, 2019Date of Patent: September 22, 2020Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kei Murayama
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Publication number: 20190371757Abstract: A semiconductor device includes an insulative substrate, a wiring pattern, a bonding portion, and a semiconductor element. The wiring pattern is formed on an upper surface of the insulative substrate. The bonding portion is formed on an upper surface of the wiring pattern. The semiconductor element includes an electrode pad connected to an upper surface of the bonding portion. The bonding portion includes first sintered layers distributed in the bonding portion and a second sintered layer having a density differing from each of the first sintered layers and surrounding the first sintered layer.Type: ApplicationFiled: May 30, 2019Publication date: December 5, 2019Inventor: Kei Murayama
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Patent number: 10446512Abstract: A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer.Type: GrantFiled: June 29, 2018Date of Patent: October 15, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kei Murayama
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Patent number: 10446513Abstract: A conductive ball includes a copper ball, a nickel layer covering an outer surface of the copper ball, a copper layer covering an outer surface of the nickel layer, and a tin-based solder covering an outer surface of the copper layer. A copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %.Type: GrantFiled: June 29, 2018Date of Patent: October 15, 2019Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kei Murayama
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Publication number: 20190013286Abstract: A conductive ball includes a copper ball, a nickel layer covering an outer surface of the copper ball, a copper layer covering an outer surface of the nickel layer, and a tin-based solder covering an outer surface of the copper layer. A copper weight of the copper layer relative to a summed weight of the tin-based solder and the copper layer is 0.7 wt % to 3 wt %.Type: ApplicationFiled: June 29, 2018Publication date: January 10, 2019Inventor: Kei Murayama
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Publication number: 20190013285Abstract: A conductive ball includes a copper ball, a nickel layer formed with being patterned on an outer surface of the copper ball, and a tin-based solder covering each outer surface of the copper ball and the nickel layer.Type: ApplicationFiled: June 29, 2018Publication date: January 10, 2019Inventor: Kei Murayama
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Patent number: 9802503Abstract: In order to manage power exchanged between an electric vehicle 1 and a house system 2 including an electric device 22, a power management device includes a vehicle detection portion 26 configured to detect a vehicle available for a resident of the house. A controller 24 determines power supplied from the electric vehicle 1 to the house system 2 in accordance with the presence of the vehicle detected by the vehicle detection portion 26. The power management device can thereby supply power from an electric vehicle to a house while securing the situation where the resident can move by vehicle in emergencies.Type: GrantFiled: November 8, 2012Date of Patent: October 31, 2017Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventor: Kei Murayama
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Patent number: 9716053Abstract: A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, and a heat dissipation component arranged on the wiring substrate. The heat dissipation component includes a cavity that accommodates the semiconductor element and includes an inner surface opposing the wiring substrate. The semiconductor element is located between the inner surface of the cavity and the wiring substrate. A heat conductor is bonded to the semiconductor element and to the inner surface of the cavity. The heat conductor includes linear heat conductive matters arranged between the semiconductor element and the heat dissipation component. A first alloy layer bonded to the semiconductor element covers lower ends of the heat conductive matters. The heat dissipation component includes a through hole extending through the heat dissipation component toward the heat conductor from a location outside of the heat conductor in a plan view.Type: GrantFiled: April 23, 2015Date of Patent: July 25, 2017Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Murayama, Yoshihiro Ihara
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Patent number: 9633964Abstract: A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion formed in the outermost wiring layer, the dummy wiring portion connecting the connection pad and the dummy pad. The maximum width of each of the connection pad and the dummy pad is set to be larger than the width of the dummy wiring portion. A bump of an electronic component is flip-chip connected to a connection pad through a resin-containing solder.Type: GrantFiled: February 1, 2016Date of Patent: April 25, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kei Murayama
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Patent number: 9591742Abstract: There is provided an interposer for cooling an electronic component. The interposer includes: a substrate body having a hollow cooling channel therein, wherein a cooling medium flows through the cooling channel, the cooling channel including: a plurality of main cooling channels extending in a certain direction and separated from each other; an inflow channel which is communicated with one end of the respective main cooling channels; and an outflow channel which is communicated with the other end of the respective main cooling channels, and a plurality of through electrode groups each comprising a plurality of through electrodes arranged in a line. Each of the though electrodes is formed through the substrate body to reach the first and second surfaces of the substrate body. The respective through electrode groups are partitioned by at least corresponding one of the main cooling channels.Type: GrantFiled: May 30, 2014Date of Patent: March 7, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei Murayama, Mitsutoshi Higashi, Koji Nagai, Hideaki Sakaguchi
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Patent number: 9496725Abstract: A control apparatus includes: a target value obtaining unit obtaining a total target value of power to be discharged from storage batteries; an SOH obtaining unit obtain information on a state of health for each of the storage batteries; a charge control unit determining how the power of the total target value is divided among and discharged from each of the storage battery. The charge control unit (i) compares the state of health of a first storage battery and the state of health of a second storage battery, and, in the case where the state of health of the second storage battery is higher than the state of health of the first storage battery, (ii) discharges from the second storage battery second power lower than first power which is discharged from the first storage battery.Type: GrantFiled: March 27, 2012Date of Patent: November 15, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tomomi Katou, Minoru Takazawa, Takahiro Kudoh, Kei Murayama
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Publication number: 20160276301Abstract: A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion formed in the outermost wiring layer, the dummy wiring portion connecting the connection pad and the dummy pad. The maximum width of each of the connection pad and the dummy pad is set to be larger than the width of the dummy wiring portion. A bump of an electronic component is flip-chip connected to a connection pad through a resin-containing solder.Type: ApplicationFiled: February 1, 2016Publication date: September 22, 2016Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventor: Kei MURAYAMA
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Patent number: 9425892Abstract: The present disclosure relates to an information processing apparatus, an information processing method, and a program which are capable of swiftly starting wireless data communication between a pair of electronic devices. An information processing apparatus as one aspect of the present disclosure includes an information management unit for categorizing setting information that is obtained as a result of a connection setting process for performing wireless data communication between electronic devices as preferred information that is not deleted at a time of an initialization process or as non-preferred information that is deleted at a time of the initialization process, and managing the setting information. The present disclosure may be applied to electronic devices provided with a bluetooth interface.Type: GrantFiled: October 7, 2013Date of Patent: August 23, 2016Assignee: SONY CORPORATIONInventors: Kei Murayama, Masataka Hasegawa, Masahiro Shimizu, Satoru Osugi