Patents by Inventor Kei Takehara
Kei Takehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8748261Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.Type: GrantFiled: October 26, 2011Date of Patent: June 10, 2014Assignee: Renesas Electronics CorporationInventor: Kei Takehara
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Patent number: 8609493Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.Type: GrantFiled: June 19, 2012Date of Patent: December 17, 2013Assignee: Renesas Electronics CorporationInventors: Hideo Yamamoto, Kei Takehara
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Publication number: 20120282745Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.Type: ApplicationFiled: June 19, 2012Publication date: November 8, 2012Inventors: Hideo Yamamoto, Kei Takehara
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Patent number: 8222109Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.Type: GrantFiled: April 14, 2010Date of Patent: July 17, 2012Assignee: Renesas Electronics CorporationInventors: Hideo Yamamoto, Kei Takehara
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Publication number: 20120043603Abstract: A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.Type: ApplicationFiled: October 26, 2011Publication date: February 23, 2012Applicant: Renesas Electronics CorporationInventor: Kei Takehara
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Patent number: 8071445Abstract: In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.Type: GrantFiled: April 20, 2010Date of Patent: December 6, 2011Assignee: Renesas Electronics CorporationInventor: Kei Takehara
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Patent number: 7863679Abstract: A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode layer to provide insulation.Type: GrantFiled: October 22, 2007Date of Patent: January 4, 2011Assignee: Renesas Electronics CorporationInventor: Kei Takehara
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Publication number: 20100273304Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.Type: ApplicationFiled: April 14, 2010Publication date: October 28, 2010Inventors: Hideo YAMAMOTO, Kei TAKEHARA
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Publication number: 20100270613Abstract: In a transistor region, a source interconnect layer and a gate electrode are buried in trenches. A source extending region is provided adjacent to the transistor region or in the transistor region, and a source interconnect layer is designed to protrude from the upper end of a trench. This source interconnect layer is connected to a source electrode formed in the transistor region immediately above the trench. A gate extending region is provided outside the source extending region, and the gate electrode and a gate interconnect layer are connected. The gate electrode is formed by performing etchback without forming a resist pattern, after a polysilicon film is formed. Here, the polysilicon film remains like a side-wall on the sidewall of the portion of the source interconnect layer protruding from the upper end of the trench.Type: ApplicationFiled: April 20, 2010Publication date: October 28, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Kei Takehara
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Publication number: 20080093665Abstract: A vertical power MOSFET includes a semiconductor substrate including a trench, a gate electrode layer having a prescribed impurity concentration and being formed inside the trench, and a cap insulating layer having a lower impurity concentration than the impurity concentration of the gate electrode layer and covering the gate electrode layer to provide insulation.Type: ApplicationFiled: October 22, 2007Publication date: April 24, 2008Inventor: Kei Takehara
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Patent number: 5340459Abstract: A reactive sputtering system is provided with a side gas distribution pipe for introducing a reactive gas and argon gas into a reaction chamber and a ring-shaped gas distribution pipe for introducing the argon gas or reactive gas into the reaction chamber independently of the side gas distribution pipe, whereby the concentration of the reactive gas can be controlled with respect to a target in the diameter direction thereof to equalize the reaction between the reactive gas and the target material above the surface of the target and thus to provide an improved uniformity of the quality film.Type: GrantFiled: November 19, 1992Date of Patent: August 23, 1994Assignee: NEC CorporationInventor: Kei Takehara