Abstract: In a case where the coating film is confirmed to remain in a third step, at least one or more of conditions of the shot peening treatment including a propelling speed of the shot medium, a propelling time of the shot medium, a material of the shot medium, and an average particle diameter of the shot medium are changed and the second step and the third step are repeated until the coating film does not remain In a case where the coating film is not confirmed to remain in the third step, the condition of the shot peening treatment in the second step in which the coil spring is obtained with no remaining coating film is determined as the propelling condition for the shot medium.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

Abstract: To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a ground plane region of an n-type MISFET is formed by ion-implanting a p-type impurity and nitrogen (N) and a ground plane region of a p-type MISFET is formed by ion-implanting an n-type impurity and one of carbon (C) and fluorine (F).

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

Abstract: To make a gate insulating film of a selecting transistor coupled in series to a MONOS memory transistor thinner and to ensure insulation resistance of the gate insulating film, the selecting transistor and the memory transistor, which constitute a memory cell, are formed on an SOI substrate, and an extension region of the selecting transistor is formed to be away from a selecting gate electrode in a plan view. A drain region of the selecting transistor and a source region of the memory transistor share the same semiconductor region with each other.

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract: A semiconductor device includes an SOI substrate and an anti-fuse element formed on the SOI substrate. The SOI substrate has a p type well region formed on a main surface side of a support substrate and an SOI layer formed on the p type well region via a BOX layer. The anti-fuse element has a gate electrode formed on the SOI layer via agate insulating film. The anti-fuse element constitutes a storage element, and a first potential is applied to the gate electrode and a second potential of the same polarity as the first potential is applied to the p type well region in a write operation of the storage element.

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract: High strength steel wire for spring containing, by mass %, C: 0.67% to less than 0.75%, Si: 2.0 to 2.5%, Mn: 0.5 to 1.2%, Cr: 0.8 to 1.3%, V: 0.03 to 0.20%, Mo: 0.05 to 0.25%, W: 0.05 to 0.30%, and N: 0.003 to 0.007%, having a total of contents of Mn and V of 0.70%?Mn+V?1.27% and a total of contents of Mo and W of 0.13%?Mo+W?0.35%, limiting P: 0.025% or less, S: 0.025% or less, and Al: 0.003% or less, and having a balance of iron and unavoidable impurities, having a microstructure comprised of, by volume percent, over 6% to 15% of retained austenite and tempered martensite, having a prior-austenite grain size number of 10 or more, having a density of presence of spheroidal carbides with a circle equivalent diameter of 0.2 to 0.5 ?m of 0.06 particles/?m2 or less, having a density of presence of spheroidal carbides with a circle equivalent diameter of over 0.5 ?m of 0.01 particles/?m2 or less, and having a tensile strength of 2100 to 2350 MPa.

Abstract: An object is to provide a semiconductor device having improved reliability by preventing, in forming a nonvolatile memory and MOSFETS on the same substrate, an increase in the size of grains in a gate electrode. The object can be achieved by forming the control gate electrode of the nonvolatile memory and the gate electrodes of the other MOSFETs from films of the same layer, respectively, and configuring each of the control gate electrode and the gate electrodes from a stack of two polysilicon film layers.

Abstract: Abrasion resistance is further enhanced in a sliding member used in an internal combustion engine. With respect to a valve lifter 6 used in an internal combustion engine 100, hard particles having higher hardness than the valve lifter 6 are dispersed onto the top face 61 of the valve lifter 6, and a nitriding treatment is conducted on the top face 61 dispersed with the hard particles.

Abstract: It is a technical common knowledge that a chaplet used in casting of a hollow casting is fusion-bonded with the melt and is incorporated into the casting. However, the adhesion between the chaplet and the casting body is not necessarily satisfactory, thereby incurring the strength reduction of a thin-wall hollow casting. A core for a thin-wall hollow casting according to the present invention is provided with a chaplet mounted thereon. The chaplet has arcuate portion 2 with a gap 5 and a plurality of projections 4 from an outer peripheral of the arcuate portion and is in contact with an inner wall 7 of a mold. The entire arcuate portion of the chaplet is included in a groove 6 formed around an outer peripheral portion of the core body. Only the projections 4 of the chaplet protrude from the core body, when the chaplet is inserted in the groove.

Abstract: High strength steel wire for spring containing, by mass %, C: 0.67% to less than 0.75%, Si: 2.0 to 2.5%, Mn: 0.5 to 1.2%, Cr: 0.8 to 1.3%, V: 0.03 to 0.20%, Mo: 0.05 to 0.25%, W: 0.05 to 0.30%, and N: 0.003 to 0.007%, having a total of contents of Mn and V of 0.70%?Mn+V?1.27% and a total of contents of Mo and W of 0.13%?Mo+W?0.35%, limiting P: 0.025% or less, S: 0.025% or less, and Al: 0.003% or less, and having a balance of iron and unavoidable impurities, having a microstructure comprised of, by volume percent, over 6% to 15% of retained austenite and tempered martensite, having a prior-austenite grain size number of 10 or more, having a density of presence of spheroidal carbides with a circle equivalent diameter of 0.2 to 0.5 ?m of 0.06 particles/?m2 or less, having a density of presence of spheroidal carbides with a circle equivalent diameter of over 0.5 ?m of 0.01 particles/?m2 or less, and having a tensile strength of 2100 to 2350 MPa.