Patents by Inventor Keiichi Okabe

Keiichi Okabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176252
    Abstract: An intrusion prevention device includes a reception unit, a monitoring unit, and a determination unit. The reception unit receives, from a control target device, a notification indicating a state of the control target device. The monitoring unit receives a control command transmitted from a control device to the control target device. The determination unit determines whether to permit or block passage of the control command received by the monitoring unit in accordance with the state of the control target device received by the reception unit.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: November 16, 2021
    Assignees: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Keiichi Okabe, Takaaki Koyama, Jun Miyoshi, Yoshihiro Itoh, Naohiko Yoshizumi, Tetsuo Takahashi, Yuki Mori, Toshiyuki Yamada, Naoki Yamasaki
  • Publication number: 20200175160
    Abstract: The present invention reduces the time required for inspecting packets and detecting unauthorized commands. An intrusion prevention device (3) is connected to a communication network (9-1) in which a packet including a command for a device to be controlled is transmitted according to a predetermined rule. An analysis table storage part (34) stores an analysis table comprised of a predetermined number of slots for storing a predetermined number of commands together with time information. An input part (31) extracts the command from the packet detected from the communication network (9-1). A parse part (32) inserts the command into the analysis table. An analysis part (33) analyzes whether or not the plurality of commands stored in the respective slots of the analysis table follow the predetermined rule. A notification part (35) outputs an alarm when an analysis result indicates an abnormality. An output part (36) determines whether to pass or discard the packet according to the analysis result.
    Type: Application
    Filed: July 20, 2018
    Publication date: June 4, 2020
    Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Keiichi OKABE, Hiroki ITOH
  • Publication number: 20190294794
    Abstract: An intrusion prevention device includes a reception unit, a monitoring unit, and a determination unit. The reception unit receives, from a control target device, a notification indicating a state of the control target device. The monitoring unit receives a control command transmitted from a control device to the control target device. The determination unit determines whether to permit or block passage of the control command received by the monitoring unit in accordance with the state of the control target device received by the reception unit.
    Type: Application
    Filed: September 26, 2017
    Publication date: September 26, 2019
    Applicants: NIPPON TELEGRAPH AND TELEPHONE CORPORATION, MITSUBISHI HEAVY INDUSTRIES, LTD.
    Inventors: Keiichi OKABE, Takaaki KOYAMA, Jun MIYOSHI, Yoshihiro ITOH, Naohiko YOSHIZUMI, Tetsuo TAKAHASHI, Yuki MORI, Toshiyuki YAMADA, Naoki YAMASAKI
  • Patent number: 9093498
    Abstract: The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: July 28, 2015
    Assignee: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Keiichi Okabe, Susumu Miyazaki
  • Patent number: 7810383
    Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: October 12, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Keiichi Okabe, Hisakazu Takano, Daisuke Nakamata
  • Patent number: 7727860
    Abstract: The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.
    Type: Grant
    Filed: May 18, 2006
    Date of Patent: June 1, 2010
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Susumu Miyazaki, Tokio Takei, Keiichi Okabe
  • Publication number: 20090233109
    Abstract: The present invention is a method for producing a bonded wafer, comprising at least: bonding a base wafer serving as a support substrate to a bond wafer made of a silicon single crystal via an insulator film or directly bonding the wafers to provide a bonded wafer; and reducing a thickness of the bond wafer to form a thin film made of the silicon single crystal on the base wafer, wherein the thickness of the bonded wafer is reduced based on at least surface grinding while measuring the thickness of the bond wafer, and surface grinding with respect to the bond wafer is stopped when the thickness of the bond wafer reaches a target thickness. As a result, the method for producing a bonded wafer enabling a silicon single crystal thin film to precisely have a desired film thickness, a bonded wafer, and a surface grinding machine enabling a silicon single crystal thin film to precisely have a desired film thickness are provided.
    Type: Application
    Filed: March 29, 2006
    Publication date: September 17, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LDT.
    Inventors: Keiichi Okabe, Yoshikazu Tachikawa, Susumu Miyazaki, Sigeyuki Yoshizawa, Tokio Takei
  • Publication number: 20090111245
    Abstract: The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid.
    Type: Application
    Filed: May 18, 2006
    Publication date: April 30, 2009
    Applicant: Shin-etsu Handotai Co., Ltd.
    Inventors: Keiichi Okabe, Susumu Miyazaki
  • Publication number: 20090042363
    Abstract: The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.
    Type: Application
    Filed: May 18, 2006
    Publication date: February 12, 2009
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Susumu Miyazaki, Tokio Takei, Keiichi Okabe
  • Publication number: 20080166823
    Abstract: The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 10, 2008
    Inventors: Keiichi Okabe, Hisakazu Takano, Daisuke Nakamata
  • Patent number: 6583029
    Abstract: There are provided a method for manufacturing a mirror polished wafer with little polishing sag (peripheral sag) by a relatively easy method, a method for manufacturing a bonded wafer having an SOI layer or a bond layer which has no periphery removing region or reduces it, and a bonded wafer thereof. There is prepared a silicon wafer having chamfered portions in which when the chamfering width of the front surface side of the silicon wafer is X1 and the chamfering width of the back surface side thereof is X2, X1<X2, the front surface of the silicon wafer is mirror polished, and the front surface side thereof is chamfered again so that the chamfering width thereof is X3 (X3>X1).
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: June 24, 2003
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Takao Abe, Tokio Takei, Keiichi Okabe, Hajime Miyajima
  • Patent number: 6491836
    Abstract: A method for producing a semiconductor wafer that yields a wafer having high flatness and back surface characteristics to address problems concerning the back surface of a wafer produced by the conventional surface grinding/double side polishing method and observed during the production process. The method comprises flattening both sides of the wafer by surface grinding means, eliminating a mechanically damaged layer by an etching treatment, and then subjecting a front surface of the wafer to a single side polishing treatment, wherein a back surface of the wafer has glossiness in a range of 20-80%.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: December 10, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Sadayuki Okuni, Shunichi Ikeda, Keiichi Okabe, Hisashi Oshima
  • Patent number: 6358117
    Abstract: A surface grinding method is provided by which grinding striations are produced so that the striations can fully be removed by a polish-off amount less than required in a conventional way in mirror polishing following surface grinding using an infeed type surface grinder, in which two circular tables, opposite to each other, which are driven and rotate independently from each other, are arranged so that the peripheral end portion of one table coincides with an axial center of a rotary shaft of the other table all time, the two circular tables being located so as to be shifted sideways from each other; not only is a grinding stone held fixedly on an opposite surface of the one table, but the wafer is fixed on an opposite surface of the other table; the two tables are rotated relatively to each other; and at least one table is pressed on the other while at least one table is relatively moved in a direction, so that a surface of the wafer is ground, wherein the surface of the wafer is ground while controlling a
    Type: Grant
    Filed: November 17, 1999
    Date of Patent: March 19, 2002
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Hisashi Oshima, Keiichi Okabe
  • Patent number: 6284658
    Abstract: The present invention has an object to provide a manufacturing process of a semiconductor wafer in which improvement on accuracy in a chamfering portion is realized. The manufacturing process of a semiconductor wafer comprises: a slicing step of obtaining a wafer in the shaped of a thin disk by slicing a single crystal ingot; a surface-grinding step of flattening a surface of the wafer; a chamfering step of chamfering the peripheral edge portions; and mirror-polishing step of mirror-polishing the surface of the wafer, wherein a simultaneous double-side surface-grinding step of grinding both sides of the wafer simultaneously by a double-side grinding machine is existent prior to the chamfering step in order to remove wafer waviness and a secondary grinding step is performed by grinding a single side or simultaneously both sides of the wafer after the chamfering step is carried out, so that improvement on accuracy in a chamfered portion is realized.
    Type: Grant
    Filed: July 7, 1999
    Date of Patent: September 4, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Kato, Sadayuki Okuni, Keiichi Okabe, Hisashi Oshima
  • Patent number: 6220928
    Abstract: The present invention provides a surface grinding method and apparatus for achieving a thin plate work such as a semiconductor wafer with high flatness, high accuracy and certainty and the apparatus comprises: a surface grinder in which a grinding wheel support member 3 by which a rotary shaft 5 of a grinding wheel 6 is supported is held by a pivotal shaft portion 4 and a grinding wheel shaft inclination control motor 9 which displaces the grinding wheel support member 3 by activating the pivotal shaft portion 4 is provided; a corrective angle storage device 15 which stores a corrective angle of an inclination angle of a rotary shaft 5 of the grinding wheel 6 to a rotary shaft 13 of a wafer 12; and a shaft inclination control apparatus 14 which sends out a signal to control the grinding wheel shaft inclination control motor 9 while reading a corrective angle of the corrective angle storage device 15, wherein a relative inclination angle of the grinding wheel to the thin plate work, in a more concrete manner a
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: April 24, 2001
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Keiichi Okabe, Hisashi Oshima, Sadayuki Okuni, Tadahiro Kato
  • Patent number: D584355
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventors: Masataka Hidaka, Yukinobu Kudo, Keiichi Okabe
  • Patent number: D669533
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: October 23, 2012
    Assignee: Panasonic Corporation
    Inventors: Keiichi Okabe, Toshihiro Nakashima, Atsushi Tani