Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

Abstract: A memory system includes a plurality of nonvolatile memory chips (CHP1 and CHP2) each having a plurality of memory banks (BNK1 and BNK2) which can perform a memory operation independent of each other and a memory controller (5) which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Abstract: In an image forming apparatus, an area applied with a lubricant, i.e., an area of a lubricant layer having a uniform thickness, is obtained by spreading the lubricant by a lubricant smoothing blade. The area applied with a lubricant covers an area cleaned by a cleaning blade, i.e., a contact portion of the cleaning blade with a photoconductor.

Abstract: A flash memory 1 based on the multilevel storage technology for storing the information of two or more bits is provided with four banks 2a to 2d. For example, in the left side of the bank 2a, a data latch 6a is provided along one short side of the bank 2a, while in the right side thereof, a data latch 6b is provided along the other short side of the bank 2a. At the lower side of the data latches 6a, 6b, arithmetic circuits 7a, 7b are provided. The data latches 6a, 6b are respectively formed of SRAMs. A sense latch 5a is divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latch 5a is connected with the data latches 6a, 6b via the signal lines respectively allocated along both short sides of the bank 2a.

Abstract: A developer bearing member on which grooves slanting in a thrust direction of the developer bearing member cross other grooves reversely slanting relative to the thrust direction, wherein each of the grooves and the reversely slanting grooves is slanting at an angle of greater than 0° and not greater than 40°. Any two adjacent intersections of the grooves and the reversely slanting grooves in the thrust (or peripheral) direction are preferably on different levels in the peripheral (or thrust) direction. The distance between two adjacent intersections in the thrust direction is preferably from 1.3 mm to 4.8 mm. The distance between two adjacent intersections in the thrust direction is preferably from 0.38 Vd/Vi (mm) to 1.1 Vd/Vi (mm). The deviation in depth of grooves present on a 36° arc surface portion of the member is not greater than 15% of the gap between the image bearing member and the developer bearing member.

Abstract: An image forming apparatus includes an image bearing member configured to bear a toner image on a surface thereof. A charging mechanism is configured to uniformly charge the surface of the image bearing member. An intermediate transfer mechanism is configured to transfer the toner image from the image bearing member onto an image receiver. A cleaning mechanism is configured to clean the surface of the image bearing member after the toner image is transferred onto the image receiver. A lubricant supplying mechanism is configured to supply a lubricant contained therein onto the surface of the image bearing member and form a thin layer using a lubricating blade. The lubricant supplying mechanism is disposed between the cleaning mechanism and the charging mechanism.

Abstract: An image forming apparatus includes an image carrier configured to form a latent image and a development unit including a development member configured to develop the latent image forming on the image carrier with a developer, and a plurality of conveying members each including at least one spiral vane and configured to rotate around a spiral axis of the spiral vane to revolve and transfer the developer around the spiral axis in a direction along the spiral axis, the plurality of conveying members configured to transfer the developer sequentially from a conveying member to an adjacent conveying member and including a first conveying member arranged at a position closest to the development member to supply developer to the development member, wherein a number of the spiral vanes of the first conveying member are at least two and is also greater than the number of spiral vanes in the remaining conveying members.

Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Abstract: A method of evaluating a cell state based on information of an image taken of a cell containing a chromosome territory is provided. This method includes extracting the chromosome territory from the image (S20), standardizing a positioning state of the chromosome territory and then quantifying the positioning state (S22), and evaluating the cell state based on the quantified positioning state of the chromosome territory (S26).

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: The disclosed flash memory is provided with a majority logic circuit 3 and shift registers 61 to 63. Three out of the banks 2a to 2c of the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuit 3 performs error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer 11, thus providing highly reliable management information very quickly. The shift registers 61 to 63 delay a control signal that is output from a control circuit 12 by a certain period of time before outputting the control signal to sense amplifiers 42 to 44. This delay makes it possible to make the operating currents of the banks 2a to 2d start to flow at different times and to suppress a peak current flowing in the flash memory.

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A charging device including a charging member configured to charge an image bearing member while the charging member is contacted with or is located so as to be close to the image bearing member when the charging device is set in an image forming apparatus; and a cleaning member configured to clean a surface of the charging member while contacting the surface of the charging member, wherein the pressure A at which the cleaning member is contacted with the charging member when the charging device is set in the image forming apparatus is greater than the pressure B at which the cleaning member is contacted with the charging member before the charging device is set in the image forming apparatus.

Abstract: This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1×sense latch circuit+2×SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for “10” and “00” distributions; after the data transfer for “01” distribution, writing is done; after the data transfer for “11” distribution word disturb determination is done; and simplified upper limit determination is done in this sequence.

Abstract: A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: An image forming apparatus includes a photoconductor, a cleaning device, and a toner transporting device. The photoconductor has a toner image formed thereon. The cleaning device removes toner remaining on the photoconductor. The toner transporting device transports the toner removed by the cleaning device. The toner transporting device includes a first toner transport path forming member, a first toner transporting member, and a length control member. The first toner transporting member is partly provided in the first toner transport path forming member, expands and contracts in a length direction thereof, and transports the toner through the first toner transport path forming member. The length control member is provided at a downstream end of the first toner transport path forming member, and is pressed against the first toner transporting member to keep a constant length of the first toner transporting member. An image forming method is also described.

Abstract: There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases.

Abstract: A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order.

Abstract: A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside.