Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.3.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.3.

Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

Abstract: A wiring substrate for mounting semiconductors is provided with an insulation film, wires formed in the insulation film, and a plurality of electrode pads that electrically connect to the wires through vias. The electrode pads are provided to have their surfaces exposed to both of the front surface and the rear surface of the insulation film, and at least a part of the side surface of the electrode pads is buried in the insulation film. The insulation film is formed by forming electrode pads on the respective two metallic plates, thereafter, laminating an insulation layer and wires on the respective metallic plates to cover the electrode pad, and adhering the insulation layers to each other for integration, and thereafter, removing the metallic plates.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D-65/D150)?3.0 (5) H23?140 (6) (H-65/H150)?2.

Abstract: A printed circuit board is provided including a lower interconnect, a base insulating film formed on the lower interconnect, and a via hole formed on the base insulating film, and an upper interconnect connected to the lower interconnect with the via hole. The base insulating film has a thickness of about 3 to 100 &mgr;m and has a breaking strength of about 80 MPa or more at a temperature of 23° C. and when the base insulating film is defined to have a breaking strength “a” at a temperature of −65° C. and a breaking strength “b” at a temperature of 150° C., a value of a ratio (a/b) is about 4.5 or less.

Abstract: A method of producing a multilayer wiring substrate is disclosed. The multilayer wiring substrate is free from a core substrate and includes a build up layer which includes an insulator layer and a wiring layer. One of a first main surface and a second main surface of the build up layer is formed with a metal supporting frame body. The method includes the steps of: forming a first insulator layer on a first main surface of a metal supporting plate, where the first insulator layer is included in the insulator layer and becomes a first resist layer which is positioned on the first main surface's side of the build up layer, and forming a first metal pad layer in a given position on a first main surface of the first insulator layer, where the first metal pad layer is included in the wiring layer and becomes a metal pad layer.

Abstract: An infrared ray test for a semiconductor chip is conducted by irradiating infrared ray onto a bottom surface of a semiconductor chip, receiving the infrared ray reflected from a bonding pad and displaying the image of the bonding pad on a monitor. The image obtained from the infrared ray has information whether the bonding pad itself or a portion of the silicon substrate underlying the bonding pad has a defect or whether or not there is a deviation of the bonding pad with respect to the bump.

Abstract: A printed circuit board is connected to a single-layer wiring tape so as to surround an integrated circuit element which is connected to the single-layer wiring tape. Wiring patterns of the wiring tape are formed from either a power electrode or a ground electrode on the integrated circuit element to a planar metal pattern on the printed circuit board, from the planar metal pattern on the printed circuit board to either an external power terminal or an external ground terminal on the wiring tape, and from a signal electrode on the integrated circuit element to an external signal terminal on the wiring tape.

Abstract: An area TAB film has a plurality of first lead lines and a plurality of second lead lines on a base film. Each of first lead lines will be electrically connected to each of peripheral electrode pads while each of second lead lines will be electrically connected to each of inner electrode pads when the chip will be mounted on the TAB film. In this TAB film, the first and the second lead lines have a staggered arrangement from each other and are extended in opposite directions. Practically, the distance or the gap between the first lead lines is wider than that of conventional TAB film. Consequently, the TAB film can cope with an increase of the number of pads with a package size kept unchanged and serves to obtain a low cost package as compared with the conventional TAB film.

Abstract: A semiconductor device includes multilayer film carriers, a plurality of connection layers having innerleads protruded from the film carriers, and a semiconductor chip having electrode pads connected to the innerleads.

Abstract: An insulating film has conductive layers on a first surface and conductive protrusions on a second surface. The conductive layers are connected to the conductive protrusions via through holes provided in the insulating film. A semiconductor chip having pads is adhered by an adhesive layer to the insulating film. Then, the conductive layers are locally pressured, so that the conductive layers are electrically connected to respective ones of the pads.

Abstract: In a method of manufacturing a semiconductor device comprising a semiconductor chip and a carrier film which includes an insulating film and wiring patterns formed on one of main surfaces of the insulating film, an adhesive layer is formed on a surface of a semiconductor wafer having a number of integrated circuits. Each of the integrated circuits has electrode pads for external connection on the foregoing surface of the semiconductor wafer. Subsequently, openings are formed at regions of the adhesive layer corresponding to the electrode pads, and then, the semiconductor wafer is cut per integrated circuit so as to obtain the semiconductor chips. Thereafter, the electrode pads of the semiconductor chip and the wiring patterns of the carrier film are connected to each other through the corresponding openings of the adhesive layer, respectively. Then, the semiconductor chip and the carrier film are bonded together via the adhesive layer interposed therebetween.

Abstract: A process for manufacturing a semiconductor device includes defining chip sections on a wafer by scribe lines with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.