Patents by Inventor Keiichiro Shimizu

Keiichiro Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6847063
    Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh, Paul A. Clifton
  • Patent number: 6847062
    Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh
  • Publication number: 20040065875
    Abstract: In a semiconductor device functioning as a SiGeC-HBT, an emitter/base stacked portion 20 is formed on a Si epitaxially grown layer 2. The emitter/base stacked portion 20 includes: a SiGeC spacer layer 21; a SiGeC core base layer 22 containing boron at a high concentration, a SiGe cap layer 23; a Si cap layer 24, and an emitter layer 25 formed by introducing phosphorus into the Si cap layer 24 and the SiGe cap layer 23.
    Type: Application
    Filed: April 15, 2003
    Publication date: April 8, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh
  • Publication number: 20040065878
    Abstract: In a semiconductor device acting as an HBT, an emitter/base laminate portion is provided on a Si epitaxially grown layer in the SiGeC-HBT. The emitter/base laminate portion includes a SiGeC spacer layer, a SiGeC core base layer containing the boron, a Si cap layer, and an emitter layer formed by introducing phosphorous into the Si cap layer. The C content of the SiGeC spacer layer is equal to or lower than that of the SiGeC core base layer.
    Type: Application
    Filed: April 15, 2003
    Publication date: April 8, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Teruhito Ohnishi, Koichiro Yuki, Shigeki Sawada, Keiichiro Shimizu, Koichi Hasegawa, Tohru Saitoh, Paul A. Clifton
  • Patent number: 6271070
    Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Naoki Kotani, Keiichiro Shimizu
  • Publication number: 20010003660
    Abstract: On a main surface of a p-type silicon substrate having a bipolar transistor forming region and a MOS transistor forming region, an epitaxial layer is grown and n-type buried layers are formed. After forming a trench penetrating the buried layer, a buried polysilicon layer is formed in the trench. Then, a threshold control layer, a punch-through stopper layer, a channel stopper layer, an n-type well layer and a p-type well layer of each MOSFET are formed. At this point, since the well layer is formed through high energy ion implantation, the n-type buried layer is suppressed from being enlarged, and hence, time required for forming the trench can be shortened. Thus, a practical method of manufacturing a semiconductor device is provided.
    Type: Application
    Filed: December 8, 1998
    Publication date: June 14, 2001
    Inventors: NAOKI KOTANI, KEIICHIRO SHIMIZU
  • Patent number: 5317907
    Abstract: In an air conditioning apparatus, the refrigerant discharged from a compressor of an outdoor unit is passed through an outdoor heat exchanger, the refrigerant having passed through the outdoor heat exchanger is passed through an indoor heat exchanger of an ambient air-conditioning unit and the refrigerant having passed through the indoor heat exchanger is returned to the compressor to cool the whole space in the room. At the same time, the refrigerant discharged from the compressor is passed through the outdoor heat exchanger, the refrigerant having passed through the outdoor heat exchanger is passed through indoor heat exchangers of a plurality of personal air-conditioning units and the refrigerant having passed through the indoor heat exchangers is returned to the compressor to separately cool the discrete spaces in the room.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: June 7, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiichiro Shimizu, Eiji Kuwahara, Manabu Kitamoto, Masao Amano, Yasunori Ichikawa, Masayuki Hibi, Keizo Iwata
  • Patent number: 5218838
    Abstract: Two or more indoor units are provided on ceiling and floor of a room. Each of the indoor units has an air heat exchanger for cooling indoor air, and a drain pan for catching drainage produced by the air heat exchanger. A drain pipe is provided in the ceiling and under the floor. The, drainage in each of the drain pans flows into the drainage pipe. The drain in the drain pipe is carried and discharged outdoor by a drain carrying unit.
    Type: Grant
    Filed: April 23, 1992
    Date of Patent: June 15, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Manabu Kitamoto, Yasunori Ichikawa, Keiichiro Shimizu, Eiji Kuwahara, Masao Amano, Masayuki Hibi, Keizo Iwata
  • Patent number: 4521080
    Abstract: A nematic-phase liquid crystal material is sandwiched between two opposing parallel plates at least one of which is transparent. The two parallel plates are respectively coated with transparent electrode films having parallel micro-groove structures at the respective inner surfaces in contact with the nematic-phase liquid crystal material established by unidirectional rubbing. In particular, an additional or second micro-groove structure is further provided for said fist-named micro-groove structure which has an asymmetric or anisotropic profile along the longitudinal axes of the respective micro-grooves within the first micro-groove structure, preferably of a substantially saw-tooth profile. This combination results in a surface anisotropy in solid geometry rather than in plane geometry in the interfacial surfaces.
    Type: Grant
    Filed: October 18, 1982
    Date of Patent: June 4, 1985
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Fumiaki Funada, Keiichiro Shimizu
  • Patent number: 4510517
    Abstract: An electronically controlled variable semiconductor resistor having a three layer construction of either an NPN-type or a PNP-type which is similar to that of a bipolar transistor and basically using the base region and collector region of the transistor as a variable resistor having its resistance value controlled by varying its emitter current. The conductivity of the base region adjoining the emitter region and that of the collector region opposite the emitter region across the base region are modulated largely by minority carriers injected into the base region from the emitter. The carrier density at each emitter, base or collector region is reasonably controlled so as to thereby make it possible to obtain a variable resistor whose resistance value changes about in an inverse proportion to the emitter current and the electrode of proper construction is designed to allow the control signal component for controlling the emitter current not to appear at both ends of the resistor electrode at the resistor.
    Type: Grant
    Filed: December 14, 1982
    Date of Patent: April 9, 1985
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenzo Tanabe, Keiichiro Shimizu
  • Patent number: 4390245
    Abstract: An optical display cell comprising a pair of substrates at least one of which is transparent, a sealing element for sealing the pair of substrates at their peripheral portions, and an adhesive for bonding portions of the pair of substrates inboard of the sealing element. By the adhesive, the distance between the pair of substrates is maintained approximately constant. Preferably, the adhesive is composed of Nylon or the like. In addition, a spacer member can be provided for maintaining the distance between the pair of substrates approximately uniform. Preferably, the spacer member is made of glass fiber. More preferably, the adhesive is attached to one of the substrates so as to indicate a specific type of symbol such as a line, a unit, or the like.
    Type: Grant
    Filed: July 16, 1980
    Date of Patent: June 28, 1983
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keiichiro Shimizu, Wataru Horii
  • Patent number: 4386352
    Abstract: A matrix type display panel is disclosed which comprises a plurality of gate lines, a plurality of source lines normal to the gate lines, a pair of substates with one carrying a thin film transistor (TFT) array including a plurality of TFTs one for each of the intersections of the gate and source lines and the other carrying a common electrode and liquid crystal material interposed between the TFT array and the common electrode. The common electrode is supplied with the voltage of which the waveform is different between odd scanning frames and during even scanning frames. In a write mode, the source line is supplied with a pair of positive and negative pulses during the odd scanning frames and with the zero voltage during the even scanning frames. In a non-write mode, on the other hand, the source line is supplied with the zero voltage during the even scanning frames and with a pair of positive and negative pulses during the odd scanning frames.
    Type: Grant
    Filed: January 30, 1981
    Date of Patent: May 31, 1983
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Heisaku Nonomura, Keiichiro Shimizu, Kohei Kishi, Hisashi Uede
  • Patent number: 4359729
    Abstract: The disclosure is directed toward an XY matrix type liquid crystal. In the case where more than one kind of display pattern are to be displayed using substantially the same line or lines (a column or columns for a column sequential drive method), only line (or column) electrodes associated with a predetermined display are supplied with a voltage. The period of time where a voltage is applied per line or per column (that is, duty factor) is switched in accordance with a display pattern which is about to be displayed.
    Type: Grant
    Filed: October 17, 1978
    Date of Patent: November 16, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Keisaku Nonomura, Keiichiro Shimizu, Hisashi Uede
  • Patent number: 4335937
    Abstract: Within a matrix display type liquid crystal display having a first family of electrodes aligned in one direction at least the viewing side of which is made of transparent conducting material, a second family of electrodes aligned in a different direction crossed with said one direction, and a liquid crystal material between the both families of the electrodes, a respective one of the electrodes of at least one family of said both electrode families is made up of a picture element electrode and a wiring electrode for connecting the picture element electrodes and an extension electrode connected to the wiring electrode and an electrode width at a portion thereof other than a picture element area wider than the picture element are for the purpose of reducing the resistance of the wiring electrode.
    Type: Grant
    Filed: October 27, 1978
    Date of Patent: June 22, 1982
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshiaki Takamatsu, Keiichiro Shimizu, Tomio Wada, Keisaku Nonomura
  • Patent number: 4232947
    Abstract: A nematic-phase liquid crystal material is sandwiched between two opposing parallel plates at least one of which is transparent. The two parallel plates are respectively coated with transparent electrode films having parallel micro-groove structures at the respective inner surfaces in contact with the nematic-phase liquid crystal material established by unidirectional rubbing. In particular, an additional or second micro-groove structure is further provided for said first-named micro-groove structure which has an asymmetric or anisotropic profile along the longitudinal axes of the respective micro-grooves within the first micro-groove structre, preferably of a substantially saw-tooth profile. This combination results in a surface anisotropy in solid geometry rather than in plane geometry in the interfacial surfaces.
    Type: Grant
    Filed: July 1, 1975
    Date of Patent: November 11, 1980
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Fumiaki Funada, Keiichiro Shimizu