Patents by Inventor Keiji Hosotani

Keiji Hosotani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6879515
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: April 12, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Patent number: 6861314
    Abstract: There is provided, according to one embodiment of this invention, a semiconductor memory device including first memory elements to store a first state or a second state according to a change in resistance value, each of the first memory elements including one terminal and the other terminal, the first memory elements arranged parallel with each other, a first wiring connected with the one terminal of each of the first memory elements, and a second wiring formed in parallel with the first wiring and connected with the other terminal of each of the first memory elements, wherein the first state or the second state stored in one of selected from the first memory elements is read out by delivering an electric current from one of the first and second wirings via the one of selected from the first memory elements to the other of the first and second wirings.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: March 1, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Hosotani
  • Publication number: 20050035385
    Abstract: A magnetic memory device capable of achieving high reliability and superior operation characteristics of tunneling magneto-resistive (TMR) elements is provided. This magnetic memory device includes a semiconductor substrate, a transistor which is formed above the semiconductor substrate, and a TMR element which is formed on or above an interlayer dielectric film that covers the transistor of the substrate. The device also includes a first wiring line which is buried in the interlayer dielectric film and connected to a source/drain diffusion layer of the transistor, a second wiring line which is buried under the TMR element while overlying the first wiring line within the interlayer dielectric film and which is used to apply a current-created magnetic field to the TMR element during writing, and a third wiring line connected to an upper surface of the TMR element and provided to cross the second wiring line.
    Type: Application
    Filed: September 29, 2004
    Publication date: February 17, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji Hosotani, Kentaro Nakajima
  • Publication number: 20050024930
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Application
    Filed: August 26, 2004
    Publication date: February 3, 2005
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Publication number: 20050009210
    Abstract: A magnetic random access memory includes a silicon substrate, a transistor which has a gate electrode formed on the silicon substrate via a gate insulating film and diffusion layers formed in the silicon substrate, a first insulating film formed on the silicon substrate and the transistor, a multilayered interconnection formed in the first insulating film, and a magneto-resistive element formed above the first insulating film, wherein at least some of dangling bonds in the silicon substrate are terminated by silicon-deuterium bonds.
    Type: Application
    Filed: March 23, 2004
    Publication date: January 13, 2005
    Inventor: Keiji Hosotani
  • Publication number: 20050002230
    Abstract: A magnetic memory device includes magneto resistive elements which are laminated in each cell with easy axes of magnetization set in different directions, each magneto resistive elements having at least two resistance values, and first and second wirings which sandwich the magneto resistive elements and are arranged to extend in different directions from each other.
    Type: Application
    Filed: July 22, 2004
    Publication date: January 6, 2005
    Inventor: Keiji Hosotani
  • Patent number: 6829162
    Abstract: A magnetic memory device includes magneto resistive elements which are laminated in each cell with easy axes of magnetization set in different directions, each magneto resistive elements having at least two resistance values, and first and second wirings which sandwich the magneto resistive elements and are arranged to extend in different directions from each other.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: December 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Hosotani
  • Patent number: 6828641
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction differing from the first direction, and a magneto resistive element arranged between the first and second wirings and comprising a first portion and a second portion, the second portion being in contact with the second wiring and extending along the second wiring to reach an outside region positioned outside the first portion.
    Type: Grant
    Filed: September 8, 2003
    Date of Patent: December 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Kentaro Nakajima
  • Publication number: 20040233763
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction differing from the first direction, and a magneto resistive element arranged between the first and second wirings and including a first portion and a second portion, the second portion being in contact with the second wiring and extending along the second wiring to reach an outside region positioned outside the first portion.
    Type: Application
    Filed: June 30, 2004
    Publication date: November 25, 2004
    Inventors: Keiji Hosotani, Kentaro Nakajima
  • Patent number: 6803619
    Abstract: A magnetic memory device capable of achieving high reliability and superior operation characteristics of tunneling magneto-resistive (TMR) elements is provided. This magnetic memory device includes a semiconductor substrate, a transistor which is formed above the semiconductor substrate, and a TMR element which is formed on or above an interlayer dielectric film that covers the transistor of the substrate. The device also includes a first wiring line which is buried in the interlayer dielectric film and connected to a source/drain diffusion layer of the transistor, a second wiring line which is buried under the TMR element while overlying the first wiring line within the interlayer dielectric film and which is used to apply a current-created magnetic field to the TMR element during writing, and a third wiring line connected to an upper surface of the TMR element and provided to cross the second wiring line.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: October 12, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Hosotani, Kentaro Nakajima
  • Patent number: 6797536
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: September 28, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Patent number: 6795334
    Abstract: A read blocks are connected to a read bit line. The read block has MTJ elements connected in series or in parallel, or arranged by combining series and parallel connections between the read bit line and a ground terminal. The MTJ elements are stacked on a semiconductor substrate. The read bit line is arranged on the MTJ elements stacked. A write word line extending in the X-direction and a write bit line extending in the Y-direction are present near the MTJ elements in the read block.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: September 21, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihisa Iwata, Yoshiaki Asao, Keiji Hosotani, Junichi Miyamoto
  • Publication number: 20040173828
    Abstract: A magnetic memory device includes a first interconnection which runs in a first direction, a second interconnection which runs in a second direction different from the first direction, a magnetoresistive element which is arranged at the intersection of and between the first and second interconnections, and a metal layer which is connected to the magnetoresistive element and has a side surface that partially coincides with a side surface of the magnetoresistive element.
    Type: Application
    Filed: November 28, 2003
    Publication date: September 9, 2004
    Inventors: Kentaro Nakajima, Keiji Hosotani
  • Patent number: 6778426
    Abstract: A magnetic memory device includes a first resistance element formed in a memory cell unit, and at least one second resistance element and at least one third resistance element formed in a reference cell unit. The first, second, and third resistance elements store binary data by a resistance change. The second resistance element stores one of the binary data. The third resistance element stores the other of the binary data.
    Type: Grant
    Filed: August 7, 2002
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Keiji Hosotani
  • Publication number: 20040152227
    Abstract: A magnetic memory device includes first wiring which runs in the first direction, second wiring which runs in the second direction, a magneto-resistance element which is arranged at an intersection between the first and second wirings, a first yoke main body which covers at least either of the lower surface and two side surfaces of the first wring, a second yoke main body which covers at least either of the upper surface and two side surfaces of the second wiring, first and second yoke tips which are arranged on two sides of the magneto-resistance element in the first direction at an interval from the magneto-resistance element, and third and fourth yoke tips which are arranged on two sides of the magneto-resistance element in the second direction at an interval from the magneto-resistance element.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 5, 2004
    Inventors: Hiroaki Yoda, Yoshiaki Asao, Tomomasa Ueda, Minoru Amano, Tatsuya Kishi, Keiji Hosotani, Junichi Miyamoto
  • Publication number: 20040134876
    Abstract: There is provided, according to one embodiment of this invention, a semiconductor memory device comprising first memory elements to store a first state or a second state according to a change in resistance value, each of the first memory elements comprising one terminal and the other terminal, the first memory elements arranged parallel with each other, a first wiring connected with the one terminal of each of the first memory elements, and a second wiring formed in parallel with the first wiring and connected with the other terminal of each of the first memory elements, wherein the first state or the second state stored in one of selected from the first memory elements is read out by delivering an electric current from one of the first and second wirings via the one of selected from the first memory elements to the other of the first and second wirings.
    Type: Application
    Filed: January 5, 2004
    Publication date: July 15, 2004
    Inventor: Keiji Hosotani
  • Publication number: 20040109349
    Abstract: A magnetic memory device includes first wirings which run in the first direction and are divided in the second direction different from the first direction, a second wiring which runs in the second direction, and a first magneto-resistive element which is arranged across the first divided wirings near the intersection of the first and second wirings in the first memory cell region.
    Type: Application
    Filed: September 12, 2003
    Publication date: June 10, 2004
    Inventors: Kentaro Nakajima, Yoshiaki Asao, Keiji Hosotani, Masayuki Sagoi
  • Publication number: 20040095813
    Abstract: A semiconductor integrated circuit device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction, and a TMR device including a first magnetic layer, a nonmagnetic layer, and a second magnetic layer. The planar shape of the TMR device coincides with the planar shape of the crossing portion between the first wiring and the second wiring.
    Type: Application
    Filed: August 7, 2003
    Publication date: May 20, 2004
    Inventor: Keiji Hosotani
  • Publication number: 20040047199
    Abstract: A semiconductor memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction differing from the first direction, and a magneto resistive element arranged between the first and second wirings and comprising including a first portion and a second portion, the second portion being in contact with the second wiring and extending along the second wiring to reach an outside region positioned outside the first portion.
    Type: Application
    Filed: September 8, 2003
    Publication date: March 11, 2004
    Inventors: Keiji Hosotani, Kentaro Nakajima
  • Publication number: 20040047206
    Abstract: A magnetic memory device capable of achieving high reliability and superior operation characteristics of tunneling magneto-resistive (TMR) elements is provided. This magnetic memory device includes a semiconductor substrate, a transistor which is formed above the semiconductor substrate, and a TMR element which is formed on or above an interlayer dielectric film that covers the transistor of the substrate. The device also includes a first wiring line which is buried in the interlayer dielectric film and connected to a source/drain diffusion layer of the transistor, a second wiring line which is buried under the TMR element while overlying the first wiring line within the interlayer dielectric film and which is used to apply a current-created magnetic field to the TMR element during writing, and a third wiring line connected to an upper surface of the TMR element and provided to cross the second wiring line.
    Type: Application
    Filed: July 10, 2003
    Publication date: March 11, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiji Hosotani, Kentaro Nakajima