Patents by Inventor Keiji Ikeda

Keiji Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240117955
    Abstract: A lighting device includes a light emitting module and an optical element including first and second liquid crystal cells. Each of the first and second liquid crystal cells includes first and second transparent electrodes extending in a first direction and third and fourth transparent electrodes extending in a second direction. The light emitting module includes a light source, a light guide plate including an end surface into which light emitted from the light source is incident and a first surface from which the light incident into the end surface is emitted, and a prism sheet disposed opposite to the first surface. The second substrate of the first liquid crystal cell and the first substrate of the second liquid crystal cell are adjacent to each other. The first surface includes a plurality of first grooves extending in a third direction intersecting the first direction and the second direction.
    Type: Application
    Filed: November 22, 2023
    Publication date: April 11, 2024
    Inventors: Kojiro IKEDA, Takeo KOITO, Tae KUROKAWA, Keiji TAKIZAWA
  • Patent number: 11942545
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Publication number: 20240087616
    Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first and a second via wirings having different positions in a second direction. The memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring; and an electrode provided in a current path between the second transistor and the wiring. The second transistor comprises: a semiconductor layer electrically connected to the electrode and the second via wiring; and a gate electrode facing the semiconductor layer. The semiconductor layer faces at least one of surfaces on one side or the other side in the first direction of the gate electrode. The electrode includes a portion arranged with the second via wiring in a third direction.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Takafumi MASUDA, Nobuyoshi SAITO, Mutsumi OKAJIMA, Keiji IKEDA
  • Publication number: 20240081042
    Abstract: A semiconductor memory device comprises: a first memory layer; and a first via wiring and a second via wiring extending in a first direction, and having different positions from each other in a second direction. The first memory layer comprises: a first transistor electrically connected to the first via wiring; a memory portion electrically connected to the first transistor; a first wiring electrically connected to the first transistor; a second transistor electrically connected to the second via wiring and the first wiring; a first electrode electrically connected to the second transistor; and a second electrode electrically connected to the first wiring and first electrode. A length of the second electrode in the first direction is larger than one or both of a length of the first wiring in the first direction and a length of the first conductive layer in the first direction.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Applicant: Kioxia Corporation
    Inventors: Takafumi MASUDA, Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA
  • Patent number: 11921803
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for indicating location status. A computing device can receive a query from a user device, a current time, and a location for the user device. The computing device identifies results responsive to the query, including one or more business results that are each associated with a business location and operating hours. The computing device can select a subset of the business results as open results based on the operating hours of the business results, the current time, and travel times from the device location to the respective business locations. Data can be provided for a search engine results page that designates the subset of the business results as open results.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: March 5, 2024
    Assignee: GOOGLE LLC
    Inventors: Daisuke Ikeda, Ryoichi Imaizumi, Kaleigh S. Smith, Keiji Maekawa
  • Publication number: 20240038280
    Abstract: A semiconductor memory device comprises: memory layers arranged in a first direction; and a first wiring extending in the first direction. The memory layers each comprise: a memory portion; a transistor; and a second wiring. The transistor comprises: a semiconductor layer electrically connected between the memory portion and the first wiring; a gate electrode facing the semiconductor layer and electrically connected to the second wiring; and a gate insulating film provided between the semiconductor layer and the gate electrode. The semiconductor layer faces surfaces of the gate electrode on one side and the other side in the first direction. In a cross section perpendicular to the first direction and including a part of the transistor corresponding to one of the memory layers, the first wiring comprises: a first surface in contact with the transistor; and a second surface not in contact with the transistor.
    Type: Application
    Filed: March 16, 2023
    Publication date: February 1, 2024
    Applicant: Kioxia Corporation
    Inventors: Takafumi MASUDA, Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20230309294
    Abstract: A semiconductor device includes: an oxide semiconductor layer extending in a first direction; a gate electrode overlapping the oxide semiconductor layer in a second direction intersecting the first direction; a gate insulating film provided between the gate electrode and the oxide semiconductor layer; a first conductive layer provided on the oxide semiconductor layer in the first direction and containing a conductive oxide; a second conductive layer provided on the first conductive layer in the first direction and containing a metal element; a first protective film in contact with a side surface of the second conductive layer; and a second protective film in contact with at least a part of a side surface or an upper surface of the first conductive layer. The first protective film and the second protective film each contain a material having an oxygen diffusion coefficient smaller than that of the second conductive layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Mutsumi OKAJIMA, Nobuyoshi SAITO, Keiji IKEDA, Kotaro NODA, Takanori AKITA
  • Patent number: 11769810
    Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Junji Kataoka, Tomomasa Ueda, Shushu Zheng, Nobuyoshi Saito, Keiji Ikeda
  • Publication number: 20230301065
    Abstract: A semiconductor memory device includes: a plate electrode; a plurality of memory capacitors arranged along a front surface of the plate electrode; and a plurality of memory transistors electrically connected to the plurality of memory capacitors. Each memory capacitor includes: a columnar first electrode electrically connected to the memory transistor; a dielectric layer provided on an outer periphery of the first electrode; a second electrode provided on an outer periphery of the dielectric layer and electrically connected to the plate electrode; and an insulating layer provided between the first electrode and the plate electrode and containing a material that is different from a material contained in the dielectric layer.
    Type: Application
    Filed: September 1, 2022
    Publication date: September 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Mutsumi OKAJIMA, Keiji IKEDA
  • Patent number: 11569241
    Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 31, 2023
    Assignee: Kioxia Corporation
    Inventors: Hiroki Kawai, Junji Kataoka, Keiji Ikeda
  • Publication number: 20220406934
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Application
    Filed: July 27, 2022
    Publication date: December 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Patent number: 11462542
    Abstract: According to one embodiment, a semiconductor storage device includes a plurality of first wires extending in a first direction, a plurality of second wires extending in a second direction intersecting the first direction, and a plurality of first semiconductor transistors. Each first semiconductor transistor is respectively connected between one of the plurality of first wires and one of the plurality of second wires. Each first semiconductor transistor includes a gate electrode connected to the respective first wire and a channel layer on a first surface of the second wire and also a side surface of the respective second wire.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: October 4, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Masaharu Wada, Keiji Ikeda
  • Publication number: 20220302120
    Abstract: A semiconductor device of an embodiment is provided with: an oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; a first conductive layer provided at least one of positions between the first region and the first electrode or between the second region and the second electrode and containing a first metal element and at least one element of oxygen (O) or nitrogen (N); and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer and containing oxygen (O) and at least one element selected from indium (In), zinc (Zn), tin (Sn), or cadmium (Cd). The second conductive layer is thicker than the first conductive layer.
    Type: Application
    Filed: September 9, 2021
    Publication date: September 22, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Patent number: 11430886
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: August 30, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Sato, Tomomasa Ueda, Nobuyoshi Saito, Keiji Ikeda
  • Patent number: 11374130
    Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 28, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Shigeki Hattori, Tomomasa Ueda, Keiji Ikeda
  • Publication number: 20220085182
    Abstract: A semiconductor device according to an embodiment includes an oxide semiconductor layer, a gate electrode, and the gate electrode, a first electrode electrically connected to the oxide semiconductor layer, a second electrode electrically connected to the oxide semiconductor layer, a first conductive layer provided at at least one position between the oxide semiconductor layer and the first electrode and between the oxide semiconductor layer and the second electrode, the first conductive layer containing a first metal element, a first element different from the first metal element, and one of oxygen (O) or nitrogen (N), and a second conductive layer between the oxide semiconductor layer and the first conductive layer, the second conductive layer containing oxygen (O) and a second element different from both of the first metal element and the first element. The gate electrode is between the first electrode and the second electrode in the first direction.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Junji KATAOKA, Tomomasa UEDA, Shushu ZHENG, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20220085212
    Abstract: A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.
    Type: Application
    Filed: March 11, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Yuta SATO, Tomomasa UEDA, Nobuyoshi SAITO, Keiji IKEDA
  • Publication number: 20220068925
    Abstract: A semiconductor device of an embodiment includes an oxide semiconductor layer. The oxide semiconductor layer includes a metal oxide containing at least one first metal element selected from the group consisting of indium and tin and at least one second metal element selected from the group consisting of zinc, gallium, aluminum, tungsten, and silicon. The oxide semiconductor layer includes a first region in which at least one anion element selected from the group consisting of fluorine and chlorine is contained within a range of 1 atomic % or more and less than 8 atomic % in the metal oxide.
    Type: Application
    Filed: March 5, 2021
    Publication date: March 3, 2022
    Applicant: Kioxia Corporation
    Inventors: Hiroki KAWAI, Junji KATAOKA, Keiji IKEDA
  • Publication number: 20210249540
    Abstract: A semiconductor device of an embodiment includes: a first oxide semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode; a gate insulating layer provided between the third region and the gate electrode; a first electrode electrically connected to the first region; a second electrode electrically connected to the second region; and a second oxide semiconductor layer provided in at least one of a position between the first region and the first electrode and a position between the second region and the second electrode and containing indium (In), aluminum (Al), and zinc (Zn), an atomic ratio of aluminum to a sum of indium, aluminum, and zinc being 8% or more and 23% or less, and an atomic ratio of indium to the sum of indium, aluminum, and zinc being 45% or less.
    Type: Application
    Filed: August 24, 2020
    Publication date: August 12, 2021
    Applicant: Kioxia Corporation
    Inventors: Shigeki HATTORI, Tomomasa UEDA, Keiji IKEDA
  • Patent number: 11024719
    Abstract: A semiconductor device of an embodiment includes a first electrode, a second electrode, an oxide semiconductor channel, an insulation layer, an oxide layer, and a gate electrode. The oxide semiconductor channel includes a portion extending along a first direction and connects the first electrode to the second electrode. The insulation layer surrounds the oxide semiconductor channel. The oxide layer covers the oxide semiconductor channel and the insulation layer, and includes an oxide of a metal element. The gate electrode covers the oxide semiconductor channel, the insulation layer, and the oxide layer, and includes the metal element.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 1, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tomoaki Sawabe, Nobuyoshi Saito, Junji Kataoka, Tomomasa Ueda, Keiji Ikeda