Abstract: A dual port memory device has two input/output ports. These ports involve address circuits having different coordinate conversion tables. The dual port memory device can quickly respond to access signals prepared on different coordinates and is applicable for graphics processing, etc., which require high-speed memories.

Abstract: This data processing system has different kinds of microprocessors, a memory bus, a memory which is connected to the microprocessors through the memory bus, and a control circuit to selectively activate one of the microprocessors. A feature of the control circuit of this data processing system is that it has a selection controller in which a selection data item is set by the active one of the microprocessors and a selector for supplying rest mode signals to the microprocessors, excluding the one microprocessor corresponding to the content of the selection controller.

Abstract: The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of a groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

Abstract: The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

Abstract: A micro-computer system includes a memory device, a plurality of memory utilization devices such as processors, a bus connected between the memory device and the memory utilization devices for address information and data transfer therebetween, bus control lines, and an access arbitrator for preventing simultaneous accesses of memory utilization devices to the memory device. The bus control lines include two lines for transferring address transfer and write/read control information from one of the memory utilization devices to the memory device and one line for coupling an access acknowledge signal from the memory device to one of the memory utilization devices. The access arbitrator couples the access acknowledge signal to one of the memory utilization devices issuing an access request signal and disables another memory utilization device to issue the address transfer and read/write control information on the two bus control lines.