Patents by Inventor Keiji Sakamoto

Keiji Sakamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210384375
    Abstract: A method of manufacturing a light-emitting device includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming, on or above the first surface of the substrate, a semiconductor structure comprising a light-emitting layer; forming a crack inside the substrate, the crack reaching the first surface of the substrate; disposing a wavelength conversion layer on the second surface of the substrate; forming a first recess in the wavelength conversion layer by removing a first portion of the wavelength conversion layer, the first portion overlapping with the crack when viewed in a direction from the wavelength conversion layer toward the semiconductor structure, and leaving a second portion of the wavelength conversion layer between the first recess and the semiconductor structure; and cleaving the second portion along the crack.
    Type: Application
    Filed: June 8, 2021
    Publication date: December 9, 2021
    Applicant: NICHIA CORPORATION
    Inventors: Keiji SAKAMOTO, Takashi ABE, Hitoshi MINAKUCHI, Tsuyoshi ITO, Katsuyuki KAWABATA, Kenji HASHIZUME
  • Patent number: 10354996
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: July 16, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Patent number: 10295743
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Patent number: 10162110
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: December 25, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Yoshiaki Yamamoto, Shinichi Watanuki, Masaru Wakabayashi, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 10151881
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 11, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Hiroyuki Kunishima
  • Patent number: 10121958
    Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: November 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Tonegawa, Keiji Sakamoto
  • Publication number: 20180158816
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Application
    Filed: January 30, 2018
    Publication date: June 7, 2018
    Inventors: Satoshi KURA, Mitsuo NISSA, Keiji SAKAMOTO, Taichi IWASAKI
  • Patent number: 9985149
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: May 29, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 9917083
    Abstract: A first transistor required for decreasing leak current and a second transistor required for compatibility of high speed operation and low power consumption can be formed over an identical substrate and sufficient performance can be provided to the two types of the transistors respectively. Decrease in the leak current is required for the first transistor. Less power consumption and high speed operation are required for the second transistor. The upper surface of a portion of a substrate in which the second diffusion layer is formed is lower than the upper surface of a portion of the substrate where the first diffusion layer is formed.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: March 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Satoshi Kura, Mitsuo Nissa, Keiji Sakamoto, Taichi Iwasaki
  • Publication number: 20170307824
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Tatsuya USAMI, Keiji SAKAMOTO, Hiroyuki KUNISHIMA
  • Patent number: 9752648
    Abstract: Provided is a toothed belt that has satisfactory durability even under high-temperature and high-load conditions or within an oil or water environment. The toothed belt 10 comprises a belt body 13 including a tooth rubber portion 11 and a backing rubber portion 12. A surface of the tooth rubber portion 11 is covered with a facing fabric 20. The facing fabric 20 is subjected to RFL treatment, and has an outer surface 21 covered with a hardened material of a first epoxy resin. The softening point of the hardened material of the first epoxy resin is, for example, 110° C. or higher. The epoxy equivalent of the first epoxy resin is, for example, 100 to 1500 g/eq. Alternatively, the facing fabric 20 is subjected to impregnation treatment with a treatment agent including a second epoxy resin, a hardener for hardening the second epoxy resin, and a rubber component.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 5, 2017
    Assignee: Gates Corporation
    Inventors: Keiji Sakamoto, Shinji Uchigashima, Masanao Sakamoto
  • Patent number: 9739943
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Grant
    Filed: March 12, 2016
    Date of Patent: August 22, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Usami, Keiji Sakamoto, Hiroyuki Kunishima
  • Publication number: 20170068047
    Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: TATSUYA USAMI, KEIJI SAKAMOTO, YOSHIAKI YAMAMOTO, SHINICHI WATANUKI, MASARU WAKABAYASHI, TOHRU MOGAMI, TSUYOSHI HORIKAWA, KEIZO KINOSHITA
  • Publication number: 20170069769
    Abstract: A performance of a semiconductor device is improved. In a method of manufacturing a semiconductor device, a first semiconductor portion and a second semiconductor portion made of silicon are formed on a base body via an insulation layer, and a third semiconductor portion including a semiconductor layer made of germanium is formed on the second semiconductor portion. Next, an insulation film is formed above the first semiconductor portion, an opening portion reaching the first semiconductor portion from an upper surface of the insulation film is formed, and a metal silicide layer is formed on a part of an upper surface of the first semiconductor portion exposed to the opening portion.
    Type: Application
    Filed: August 23, 2016
    Publication date: March 9, 2017
    Inventors: Tatsuya USAMI, Yoshiaki YAMAMOTO, Keiji SAKAMOTO, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Patent number: 9508662
    Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: November 29, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Publication number: 20160293481
    Abstract: A rectangular optical waveguide, an optical phase shifter and an optical modulator each formed of a semiconductor layer are formed on an insulating film constituting an SOI wafer, and then a rear insulating film formed on a rear surface of the SOI wafer is removed. Moreover, a plurality of trenches each having a first depth from an upper surface of the insulating film are formed at a position not overlapping with the rectangular optical waveguide, the optical phase shifter and the optical modulator when seen in a plan view in the insulating film. As a result, since an electric charge can be easily released from the SOI wafer even when the SOI wafer is later mounted on the electrostatic chuck included in the semiconductor manufacturing apparatus, the electric charge is less likely to be accumulated on the rear surface of the SOI wafer.
    Type: Application
    Filed: March 12, 2016
    Publication date: October 6, 2016
    Inventors: Tatsuya USAMI, Keiji SAKAMOTO, Hiroyuki KUNISHIMA
  • Publication number: 20160284980
    Abstract: An object is to prevent a short failure in magnetic tunnel junction and thereby suppress a semiconductor device having a magnetic memory cell from having deteriorated reliability. First, a data reference layer and a cap layer are patterned. After formation of an oxygen-free first insulating film on their side walls, a base layer, a data recording layer, and a tunnel barrier layer are patterned. During patterning of the base layer, data recording layer, and tunnel barrier layer, adhesion of a metal substance of the data reference layer and the cap layer to the side wall of the tunnel barrier layer can be prevented because the data reference layer and the cap layer are covered by the first insulating film.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 29, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Takashi TONEGAWA, Keiji SAKAMOTO
  • Publication number: 20160247729
    Abstract: A semiconductor device includes: a first silicon section G1 which contains a p-type impurity and is a gate electrode G of a p-channel type MISFET 1P; a second silicon section G2 which contains an n-type impurity and is a gate electrode G of an n-channel type MISFET 2N; and an insulation film IF1 which is interposed between the first silicon section G1 and the second silicon section G2. Then, a silicide film is formed continuously on surfaces of the first silicon section G1, the insulation film IF1 and the second silicon section G2, and the first silicon section G1 and the second silicon section G2 are electrically connected to each other by the silicide film SIL. Impurity inter-diffusion can be prevented by the insulation film IF1.
    Type: Application
    Filed: December 5, 2013
    Publication date: August 25, 2016
    Inventor: Keiji SAKAMOTO
  • Publication number: 20160056115
    Abstract: A technique is provided which can prevent the quality of an electrical signal from degrading in an optical semiconductor device. In a cross-section perpendicular to an extending direction of an electrical signal transmission line, the electrical signal transmission line is surrounded by a shielding portion including a first noise cut wiring, second plugs, a first layer wiring, first plugs, a shielding semiconductor layer, first plugs, a first layer wiring, second plugs, and a second noise cut wiring, and the shielding portion is fixed to a reference potential. Thereby, the shielding portion blocks noise due to effects of a magnetic field or an electric field from the semiconductor substrate, which affects the electrical signal transmission line.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Publication number: 20160054521
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Application
    Filed: August 17, 2015
    Publication date: February 25, 2016
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto