Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.

Abstract: A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract: A wiring substrate includes a first insulation layer, a first wiring layer formed on the first insulation layer, and a second insulation layer stacked on the first insulation layer. The second insulation layer covers the first insulation layer and includes a filler. A third insulation layer is stacked on the second insulation layer. The third insulation layer is filler-free. A through electrode extends through the second and third insulation layers in a thicknesswise direction. A second wiring layer is stacked on the third insulation layer and the through electrode. The through electrode electrically connects the second wiring layer to the first wiring layer.

Abstract: A patterning method performed by a direct patterning apparatus, and a computer readable medium for controlling a computer of the direct patterning apparatus to perform the pattering method. The patterning method forms a desired pattern on the surface of the object by exposing the surface of the object to light by using a plurality of spatial light modulation elements installed in a direction perpendicular to the relative moving direction of the object, so that a defective resolution does not occur on the surface of the object.

Abstract: In a patterning apparatus for forming a desired pattern on a surface of an object by exposing the surface of the object to light by using a plurality of spatial light modulation elements assigned to respective exposure areas defined along a relative moving direction of the object, predetermined areas which are on the surface of the object and are to be positioned in the vicinity of borders of the respective exposure areas exposed to light by the spatial light modulation elements are exposed to light by the spatial light modulation elements corresponding to the exposure areas, after the object is shifted in a direction perpendicular to the relative moving direction, such that the predetermined areas are positioned in the vicinity of the center parts of the exposure areas.

Abstract: A sizing processing system according to the present invention generates an offset figure based on an offset point set obtained by offsetting the respective sides of a source figure by a distance equal to a prescribed sizing amount. When an inside-out side is detected on the offset figure, two sides of the source figure that intersect at a vertex thereof associated with the detected inside-out side are translated by a distance equal to the prescribed sizing amount, and the respective end points of the thus translated sides corresponding to that vertex are taken as offset points. Then, the offset points are added to the offset point set to generate an offset figure that does not entail the generation of an inside-out side. This can also address the problem of an inside-out side that occurs when an edge cut is inserted in the offset figure.

Abstract: In the method of converting-to-array according to the present invention, array configuration data is created by classifying the patterns congruent with a master pattern, which is a reference graphic for repetition, in the patterns arranged as mask patterns of a LSI, so that the number of the repetitions of the congruent pattern is the largest one when the congruent pattern is arranged repeatedly with a predetermined repetition pitch.

Abstract: The invention relates to a reduction processing method including a step for eliminating an “inside-out side”, contained in the sides of an offset figure generated by sizing a source figure. The inside-out side detected by the presence of a first intersection point at which adjacent offset locus line segments intersect. The step includes i) deleting the offset vertices each of which is located at one end of one of the offset locus line segments intersecting at the first intersection point, and ii) revising the offset figure by finding a second intersection point at which offset figure line segments, which form the offset figure by joining the offset vertices, intersect each other, and by setting the second intersection point at the position of the detected offset vertices as an offset vertex.

Abstract: A method of processing a figure and a recorded medium are used to obtain an enlarged figure or a reduced figure by moving the sides of a polygon, which is composed by putting a plurality of horizontal trapezoids upon each other, each of the trapezoids having upper and lower sides parallel to the X-axis, in the direction of the Y-axis to the outside or inside of the polygon in parallel with each other. The method comprises the steps of: selecting an objective horizontal trapezoid, extracting first, second and third groups of segments regarding the objective, lower and upper horizontal trapezoids, creating new first, second and third groups of segments moved to outside or inside of the polygon, removing unnecessary groups of segments, sorting the contact point and the division point, drawing parallel lines parallel to X-axis from the contact and division points, and storing the contact and division points included in the parallel line.

Abstract: This invention relates to a process for machining resin film for a wiring board or double-sided carrier tape which comprises forming openings in the resin film by applying a continuous-wave carbon dioxide gas laser beam which is scanned in one or two ways to the resin film or a laminate containing a layer of the resin film placed on a worktable (5) moving in the direction nearly at a right angle to the scanning direction of the laser beam (7). As a continuous-wave carbon dioxide gas laser beam is used for drilling holes, the operation is highly efficient and accurate and gives rigid-flex wiring boards or double-sided carrier tapes of good quality in high yield.

Abstract: A sizing processing system according to the present invention generates an offset figure based on an offset point set obtained by offsetting the respective sides of a source figure by a distance equal to a prescribed sizing amount. When an inside-out side is detected on the offset figure, two sides of the source figure that intersect at a vertex thereof associated with the detected inside-out side are translated by a distance equal to the prescribed sizing amount, and the respective end points of the thus translated sides corresponding to that vertex are taken as offset points. Then, the offset points are added to the offset point set to generate an offset figure that does not entail the generation of an inside-out side. This can also address the problem of an inside-out side that occurs when an edge cut is inserted in the offset figure.

Abstract: In the method of converting-to-array according to the present invention, array configuration data is created by classifying the patterns congruent with a master pattern, which is a reference graphic for repetition, in the patterns arranged as mask patterns of a LSI, so that the number of the repetitions of the congruent pattern is the largest one when the congruent pattern is arranged repeatedly with a predetermined repetition pitch.

Abstract: The invention relates to a reduction processing method including a step for eliminating an “inside-out side”, contained in the sides of an offset figure generated by sizing a source figure. The inside-out side detected by the presence of a first intersection point at which adjacent offset locus line segments intersect. The step includes i) deleting the offset vertices each of which is located at one end of one of the offset locus line segments intersecting at the first intersection point, and ii) revising the offset figure by finding a second intersection point at which offset figure line segments, which form the offset figure by joining the offset vertices, intersect each other, and by setting the second intersection point at the position of the detected offset vertices as an offset vertex.

Abstract: A laminate comprising at least two layers of a photosensitive resin layer and a polyimide precursor resin layer; a process for formation of an insulating protective layer using a laminate which comprises laminating a laminate comprising at least photosensitive resin layer and a polyimide precursor resin layer on an insulating board having an exposed circuit; selectively exposing the photosensitive resin layer to active light; developing the resultant photosensitive resin layer; removing the exposed polyimide precursor resin layer by etching it with an alkaline solution using the photosensitive resin layer as a mask; removing the photosensitive resin layer; and then curing the residual polyimide precusor resin layer; and a process for preparation of a printed circuit which comprises forming a polymide precursor resin layer on an insulating board having an exposed circuit, patterning the resin layer with an alkaline solution, and then curing it.