Abstract: A constructed unit is fixed to a base by means of a plurality of support posts while being spaced from the base. The constructed unit includes an orthogonal acceleration unit. An incidence regulator unit is fixed to the base by a pair of support posts while being spaced from the base and the constructed unit. The incidence regulator unit includes, among others, a pair of blades that define a slit, and heaters for heating the pair of blades.

Abstract: A testing apparatus according to an embodiment includes a chamber, a probe card including probes exposed in the chamber, a stage supporting a test target object in the chamber, a moving mechanism to move the stage between a testing position where the test target object is in contact with the probes and a cleaning position where the test target object is arranged away from the probes in a horizontal direction, and an air tube introducing first dry air into the chamber through the probe card when the stage is placed at the cleaning position.

Abstract: A constructed unit is fixed to a base by means of a plurality of support posts while being spaced from the base. The constructed unit includes an orthogonal acceleration unit. An incidence regulator unit is fixed to the base by a pair of support posts while being spaced from the base and the constructed unit. The incidence regulator unit includes, among others, a pair of blades that define a slit, and heaters for heating the pair of blades.

Abstract: A semiconductor memory device includes an n-type source/drain formed in a surface region of a p-type active region, and a gate. The semiconductor memory device also includes a withstand voltage improvement layer provided with a preset distance maintained from at least one end of the source/drain. N-type impurities are diffused in the withstand voltage improvement layer, and a withstand voltage improvement voltage is applied to the withstand voltage improvement layer to expand a depletion layer to reach the source/drain, so that the maximum withstand voltage value of a transistor is increased.

Abstract: A voltage-variable type memory element having an electrode; a charge storage layer that is arranged on the electrode via a first interlayer insulating layer and stores charges; and a semiconductor wiring which has electric conductivity, that is arranged on the charge storage layer via a second interlayer insulating layer, and comprises a region facing the charge storage layer, a resistance value of the region being variable according to magnitude of potential corresponding to an amount of charges stored in the charge storage layer, and a voltage value of a reading signal supplied and passing through the semiconductor wiring being varied according to the resistance value. A semiconductor memory device configure to a memory cell array in which voltage-variable type memory elements are arranged as memory cells.

Abstract: The semiconductor wiring has the N-well layer of the impurity layer in the P substrate formed in the region where the poly wiring and P substrate face each other, wherein the N-well layer is electrically floating, is not used as a circuit element, and does not input or output signals.

Abstract: A semiconductor memory device includes an n-type source/drain formed in a surface region of a p-type active region, and a gate. The semiconductor memory device also includes a withstand voltage improvement layer provided with a preset distance maintained from at least one end of the source/drain. N-type impurities are diffused in the withstand voltage improvement layer, and a withstand voltage improvement voltage is applied to the withstand voltage improvement layer to expand a depletion layer to reach the source/drain, so that the maximum withstand voltage value of a transistor is increased.

Abstract: A testing apparatus according to an embodiment includes a chamber, a probe card including probes exposed in the chamber, a stage supporting a test target object in the chamber, a moving mechanism to move the stage between a testing position where the test target object is in contact with the probes and a cleaning position where the test target object is arranged away from the probes in a horizontal direction, and an air tube introducing first dry air into the chamber through the probe card when the stage is placed at the cleaning position.

Abstract: A probe card includes a probe; and a probe card substrate which includes a first member and a second member, the first member having a first surface provided with the probe and the second member having a second surface surrounding the first surface, wherein a direction of the first surface is different from a direction of the second surface.

Abstract: A probe card comprises a probe; and a probe card substrate which includes a first member and a second member, the first member having a first surface provided with the probe and the second member having a second surface surrounding the first surface, wherein a direction of the first surface is different from a direction of the second surface.