Patents by Inventor Keiko Kawamura

Keiko Kawamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11222966
    Abstract: A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: January 11, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Keiko Kawamura, Tomoko Matsudai, Yoko Iwakaji
  • Publication number: 20210305366
    Abstract: A semiconductor device has a cell part and a terminal part set in the device. The terminal part encloses the cell part. The semiconductor device includes a first electrode, a first semiconductor layer of a first conductive type, a second semiconductor layer of a second conductive type, and an insulating layer. The first semiconductor layer is formed above the first electrode. The second semiconductor layer is provided in an upper portion of the first semiconductor layer, and has an impurity concentration profile along a vertical direction including a plurality of peaks. The insulating layer is provided on the second semiconductor layer.
    Type: Application
    Filed: July 29, 2020
    Publication date: September 30, 2021
    Inventors: Keiko Kawamura, Tomoko Matsudai, Yoko Iwakaji, Kaori Fuse
  • Publication number: 20210296477
    Abstract: A semiconductor device includes a semiconductor part, first and second electrodes. The semiconductor part includes first to third layers. The first electrode is provided on a back surface of the semiconductor part. The second electrode is provided on a front surface of the semiconductor part. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The third layer of the second conductivity type is provided between the second layer and the second electrode. The second electrode includes a buried contact portion and a surface contact portion. The buried contact portion extends into the second layer from the front surface of the semiconductor part and contacts the second layer. The surface contact portion contacts the third layer at the front surface of the semiconductor part.
    Type: Application
    Filed: September 4, 2020
    Publication date: September 23, 2021
    Inventors: Tomoko Matsudai, Hiroko Itokazu, Keiko Kawamura, Yoko Iwakaji, Kaori Fuse
  • Publication number: 20210296459
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Application
    Filed: June 4, 2021
    Publication date: September 23, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko IWAKAJI, Tomoko MATSUDAI, Keiko KAWAMURA
  • Patent number: 11063130
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 13, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko Iwakaji, Tomoko Matsudai, Keiko Kawamura
  • Publication number: 20210091193
    Abstract: According to an embodiment a semiconductor device includes a semiconductor layer including first trenches and second trenches, a first gate electrode in the first trench, a second gate electrode in the second trench, a first gate electrode pad, a second gate electrode pad, a first wiring connecting the first gate electrode pad and the first gate electrode, and a second wiring connecting the second gate electrode pad and the second gate electrode. The semiconductor layer includes a first connection trench. Two first trenches adjacent to each other are connected to each other at end portions by the first connection trench. At least one of the second trenches is provided between the two first trenches. The second gate electrode in the at least one second trench is electrically connected to the second wiring between the two first trenches.
    Type: Application
    Filed: February 14, 2020
    Publication date: March 25, 2021
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yoko IWAKAJI, Tomoko MATSUDAI, Keiko KAWAMURA
  • Publication number: 20210066480
    Abstract: A semiconductor device includes first and second electrodes. A first-type layer is between the first and second electrodes. A pair of first gate electrodes is between the first and second electrodes and each is surrounded by a gate insulating film. Second gate electrodes are disposed between the pair of first gate electrodes. A second-type layer is on the first-type layer in a first region between a first gate electrode and one of the second gate electrodes. Another first-type layer is on the second-type layer. This other first-type layer is directly adjacent to the gate insulating film. Another second-type layer is on the other second-type layer. A width of the first-type layer between adjacent second gate electrodes is less than a length of the first-type layer in the region between adjacent second gate electrodes.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 4, 2021
    Inventors: Keiko KAWAMURA, Tomoko MATSUDAI, Yoko IWAKAJI
  • Patent number: 10916644
    Abstract: A semiconductor device includes a first electrode, a second electrode disposed at a position opposing the first electrode, and a semiconductor body provided between the first electrode and the second electrode. The semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a third semiconductor layer of the second conductivity type; the second semiconductor layer is provided between the first semiconductor layer and the first electrode; and the third semiconductor layer is selectively provided inside the first semiconductor layer and disposed at a position separated from the second semiconductor layer. The first electrode is electrically connected to the second semiconductor layer and includes an extension portion; and the extension portion pierces the second semiconductor layer, extends in a first direction toward the second electrode, and is connected to the third semiconductor layer.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: February 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Keiko Kawamura, Tsuneo Ogura
  • Publication number: 20200091324
    Abstract: A semiconductor device includes a first electrode, a second electrode disposed at a position opposing the first electrode, and a semiconductor body provided between the first electrode and the second electrode. The semiconductor body includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type and a third semiconductor layer of the second conductivity type; the second semiconductor layer is provided between the first semiconductor layer and the first electrode; and the third semiconductor layer is selectively provided inside the first semiconductor layer and disposed at a position separated from the second semiconductor layer. The first electrode is electrically connected to the second semiconductor layer and includes an extension portion; and the extension portion pierces the second semiconductor layer, extends in a first direction toward the second electrode, and is connected to the third semiconductor layer.
    Type: Application
    Filed: January 7, 2019
    Publication date: March 19, 2020
    Inventors: Keiko Kawamura, Tsuneo Ogura
  • Patent number: 10546953
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane; a first and a second electrode; first, second, and third semiconductor regions; first and second gate electrodes in the semiconductor layer; first and second gate insulating films; and an insulating layer provided between the first and second gate electrodes and the first electrode. The first electrode has a first region and a second region. The first region contacts the semiconductor layer. The first region is located between the second region and the first semiconductor region. A first part of the first region is located between the first gate electrode and the second gate electrode. A second part of the first region is interposed between a first portion and a second portion of the insulating layer. The second part of the first region has an inverse tapered shape.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 28, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Keiko Kawamura
  • Patent number: 10510879
    Abstract: A semiconductor device includes first to third semiconductor layers stacked, and control electrodes provided in trenches extending in a stacking direction. The device further includes an insulating region and a fourth semiconductor layer. The insulating region is provided between first and second control electrodes adjacent to each other. The fourth semiconductor layer is provided between the insulating region and the first and second control electrodes, and between the insulating region and the first semiconductor layer. A first insulating film is provided between the first control electrode and the fourth semiconductor layer, and contacts the first control electrode and the fourth semiconductor layer. A second insulating film is provided between the second control electrode and the fourth semiconductor layer, and contacts the second control electrode and the fourth semiconductor layer. The insulating region has an end positioned at a level lower than a level of ends of the control electrodes.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: December 17, 2019
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Keiko Kawamura
  • Publication number: 20190296147
    Abstract: A semiconductor device includes first to third semiconductor layers stacked, and control electrodes provided in trenches extending in a stacking direction. The device further includes an insulating region and a fourth semiconductor layer. The insulating region is provided between first and second control electrodes adjacent to each other. The fourth semiconductor layer is provided between the insulating region and the first and second control electrodes, and between the insulating region and the first semiconductor layer. A first insulating film is provided between the first control electrode and the fourth semiconductor layer, and contacts the first control electrode and the fourth semiconductor layer. A second insulating film is provided between the second control electrode and the fourth semiconductor layer, and contacts the second control electrode and the fourth semiconductor layer. The insulating region has an end positioned at a level lower than a level of ends of the control electrodes.
    Type: Application
    Filed: August 21, 2018
    Publication date: September 26, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventor: Keiko KAWAMURA
  • Publication number: 20190088778
    Abstract: A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane; a first and a second electrode; first, second, and third semiconductor regions; first and second gate electrodes in the semiconductor layer; first and second gate insulating films; and an insulating layer provided between the first and second gate electrodes and the first electrode. The first electrode has a first region and a second region. The first region contacts the semiconductor layer. The first region is located between the second region and the first semiconductor region. A first part of the first region is located between the first gate electrode and the second gate electrode. A second part of the first region is interposed between a first portion and a second portion of the insulating layer. The second part of the first region has an inverse tapered shape.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 21, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Keiko Kawamura
  • Publication number: 20180286955
    Abstract: A semiconductor device includes first and second electrodes, a first semiconductor region between the first and second electrodes, a second semiconductor region between the first semiconductor region and the second electrode, a third semiconductor region between the second semiconductor region and the second electrode, a fourth semiconductor region between the third semiconductor region and the second electrode, a fifth semiconductor region between first and second portions of the fourth semiconductor region, first and second conductive regions extending inwardly of second, third and fourth semiconductor regions and insulated therefrom, an insulating region between the fourth semiconductor region and the second electrode and between the first and second conductive regions and the second electrode, and third and fourth conductive regions extending from respective first and second conductive regions inwardly of the third insulating region.
    Type: Application
    Filed: August 29, 2017
    Publication date: October 4, 2018
    Inventor: Keiko KAWAMURA
  • Publication number: 20180277667
    Abstract: A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 27, 2018
    Inventors: Hideki SEKIGUCHI, Keiko KAWAMURA, Kaori FUSE, Akira KOMATSU, Ryohei KITAO, Satoshi WAKATSUKI, Atsuko SAKATA, Koichi KUBO
  • Patent number: 9653557
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: May 16, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Yuichi Oshino, Keiko Kawamura, Bungo Tanaka
  • Patent number: 8968017
    Abstract: According to one embodiment, a semiconductor memory device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer is a first conductivity type. The second semiconductor layer is provided in a surface region of the first semiconductor layer and is the first conductivity type. The first electrode is provided inside a first trench extending in the first direction and opened to a surface of the second semiconductor layer. The second electrode is provided in a second trench extending in a second direction crossing the first direction and opened to the surface of the second semiconductor layer. A dimension from the surface of the second semiconductor layer to a lower end of the second electrode is shorter than a dimension from the surface of the second semiconductor layer to a lower end of the first electrode.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiko Kawamura, Hitoshi Kobayashi, Yusuke Kawaguchi, Shunsuke Katoh
  • Publication number: 20140374791
    Abstract: A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region having a second conductivity type, a first insulating layer on the first and second semiconductor regions, and field plate electrodes are provided in the first insulating layer at different distances from the first semiconductor layer. A first field plate electrode is at a first distance, a second field plate electrode is at a second distance greater than the first distance, and a third field plate electrode is at a distance greater than the second distance. The first through third field plate electrodes are electrically connected to each other and the third electrode is electrically connected to the second semiconductor region.
    Type: Application
    Filed: March 3, 2014
    Publication date: December 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko MATSUDAI, Yuichi OSHINO, Keiko KAWAMURA, Bungo TANAKA
  • Publication number: 20140284707
    Abstract: According to one embodiment, a semiconductor memory device includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer is a first conductivity type. The second semiconductor layer is provided in a surface region of the first semiconductor layer and is the first conductivity type. The first electrode is provided inside a first trench extending in the first direction and opened to a surface of the second semiconductor layer. The second electrode is provided in a second trench extending in a second direction crossing the first direction and opened to the surface of the second semiconductor layer. A dimension from the surface of the second semiconductor layer to a lower end of the second electrode is shorter than a dimension from the surface of the second semiconductor layer to a lower end of the first electrode.
    Type: Application
    Filed: September 11, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiko Kawamura, Hitoshi Kobayashi, Yusuke Kawaguchi, Shunsuke Katoh
  • Publication number: 20130277734
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region; a second semiconductor region having a side face and a lower face, and the faces surrounded by the first semiconductor region; a third semiconductor region provided between the second semiconductor region and the first semiconductor region; a fourth semiconductor region being in contact with an outer side face of the first semiconductor region; a plurality of first electrodes being in contact with the second semiconductor region, the third semiconductor region, and the first semiconductor region via an insulating film; a plurality of pillar areas extending from the third semiconductor region toward the fourth semiconductor region, each of the plurality of pillar areas being provided between adjacent ones of the plurality of first electrodes. An impurity density of each of the pillar areas and an impurity density of the third semiconductor region is substantially the same.
    Type: Application
    Filed: August 31, 2012
    Publication date: October 24, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshifumi NISHIGUCHI, Keiko KAWAMURA, Hideki OKUMURA, Tatsuya NISHIWAKI